diff --git a/FiltroHDL/.gitignore b/FiltroHDL/.gitignore new file mode 100644 index 0000000..dbda6ce --- /dev/null +++ b/FiltroHDL/.gitignore @@ -0,0 +1,14 @@ +_xmsgs/* +xst/* +*.cmd_log +*.lso +*.ngc +*.ngr +*.prj +*.stx +*.syr +*.xst +*.xml +*.html +*.xrpt + diff --git a/FiltroHDL/Filter.vhd b/FiltroHDL/Filter.vhd index 4211d83..cd31d10 100644 --- a/FiltroHDL/Filter.vhd +++ b/FiltroHDL/Filter.vhd @@ -1,7 +1,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -use work.array_functions.all; +use work.filter_pkg.all; entity Filter is generic ( @@ -10,7 +10,7 @@ entity Filter is SIMETRIC : boolean := TRUE; - CONSTANTS : array_of_integers := (-10,-9,-8,-7,-6,-5,-4,3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20) + CONSTANTS : array_of_integers := (-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8) ); port ( @@ -19,7 +19,8 @@ entity Filter is reset: in std_logic; d_i : in std_logic; - d_o : out std_logic + d_o : out std_logic; + p_o : out std_logic_vector(9 downto 0) ); end Filter; @@ -49,6 +50,7 @@ architecture Behavioral of Filter is signal d_s : std_logic := '0'; + signal p_s : std_logic_vector(9 downto 0) := (others => '0'); type STATUS_T is ( wait_start, clear, @@ -62,6 +64,7 @@ architecture Behavioral of Filter is begin d_o <= d_s; + p_o <= p_s; --~ Proceso sincrónico para cambio de estados stateProcess: @@ -145,6 +148,8 @@ begin begin if ( rising_edge(clk_i) ) then if ( enable = '1' and sample_clk_s = '1' and i = N-1 ) then + p_s <= std_logic_vector(to_signed(accum,p_s'length)); + if ( accum > 0 ) then d_s <= '1'; else diff --git a/FiltroHDL/FilterWrapper.vhd b/FiltroHDL/FilterWrapper.vhd index a77034b..94fa1fc 100644 --- a/FiltroHDL/FilterWrapper.vhd +++ b/FiltroHDL/FilterWrapper.vhd @@ -2,7 +2,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use work.array_functions.all; +use work.filter_pkg.all; @@ -10,55 +10,37 @@ entity FilterWrapper is generic ( CLK_FREQ : integer := 50e6; DATA_RATE: integer := 250e3; - SIMETRIC : boolean := TRUE + SIMETRIC : boolean := TRUE; + CONSTANTS : array_of_integers := (-4,-3,-2,-1,0,1,2,3,4,5) + ); port ( clk : in std_logic; ce: in std_logic; d_i : in std_logic; - d_o : out std_logic + d_o : out std_logic; + p_o : out std_logic_vector(9 downto 0) ); end FilterWrapper; architecture Behavioral of FilterWrapper is - component Filter is - - generic ( - CLK_FREQ : integer := 200e6; - DATA_RATE: integer := 250e3; - - - SIMETRIC : boolean := TRUE; - CONSTANTS : array_of_integers := (1,2,3,4,5,6,7,8,9,10) - - ); - port ( - clk_i : in std_logic; - enable: in std_logic; - reset: in std_logic; - - d_i : in std_logic; - d_o : out std_logic - ); - end component; - - begin uut: Filter Generic Map( CLK_FREQ => CLK_FREQ, DATA_RATE => DATA_RATE, SIMETRIC => SIMETRIC, - CONSTANTS => (-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20) + CONSTANTS => CONSTANTS ) PORT MAP ( clk_i => clk, enable => ce, reset => '0', d_i => d_i, - d_o => d_o + d_o => d_o, + p_o => p_o ); diff --git a/FiltroHDL/FiltroHDL.gise b/FiltroHDL/FiltroHDL.gise index 6e08ce0..f87b88f 100644 --- a/FiltroHDL/FiltroHDL.gise +++ b/FiltroHDL/FiltroHDL.gise @@ -22,10 +22,68 @@ + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FiltroHDL/FiltroHDL.xise b/FiltroHDL/FiltroHDL.xise index baad6e1..62b0689 100644 --- a/FiltroHDL/FiltroHDL.xise +++ b/FiltroHDL/FiltroHDL.xise @@ -25,7 +25,7 @@ - + diff --git a/FiltroHDL/array_functions.vhd b/FiltroHDL/filter_pkg.vhd similarity index 70% rename from FiltroHDL/array_functions.vhd rename to FiltroHDL/filter_pkg.vhd index e704b2e..3821880 100644 --- a/FiltroHDL/array_functions.vhd +++ b/FiltroHDL/filter_pkg.vhd @@ -2,8 +2,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -package array_functions is - constant MAX_RANGE : integer := 255; +package filter_pkg is + constant MAX_RANGE : integer := 511; type array_of_integers is array(integer range <>) of integer range -MAX_RANGE to MAX_RANGE; @@ -11,9 +11,33 @@ package array_functions is return integer; function reorder_array ( K : in array_of_integers ; simetric : in boolean ) return array_of_integers; + + + component Filter is + + generic ( + CLK_FREQ : integer := 200e6; + DATA_RATE: integer := 250e3; + + + SIMETRIC : boolean := TRUE; + CONSTANTS : array_of_integers := (-4,-3,-2,-1,0,1,2,3,4,5) + + ); + port ( + clk_i : in std_logic; + enable: in std_logic; + reset: in std_logic; + + d_i : in std_logic; + d_o : out std_logic; + p_o : out std_logic_vector(9 downto 0) + ); + end component; + end package; -package body array_functions is +package body filter_pkg is function array_sum ( K : in array_of_integers ) return integer is variable sum : integer := 0; @@ -51,4 +75,4 @@ package body array_functions is end if; end reorder_array; -end array_functions; +end filter_pkg; diff --git a/FiltroHDL/iseconfig/FiltroHDL.projectmgr b/FiltroHDL/iseconfig/FiltroHDL.projectmgr index 5a32b88..fec954c 100644 --- a/FiltroHDL/iseconfig/FiltroHDL.projectmgr +++ b/FiltroHDL/iseconfig/FiltroHDL.projectmgr @@ -9,13 +9,13 @@ 2 - Filter - Behavioral (/home/epilef/Proyectos/FiltroHDL/FiltroHDL/Filter.vhd) + Filter - Behavioral (/home/epilef/4-FiltroHDL/FiltroHDL/Filter.vhd) 0 0 - 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000100000000020000000000000000000000000200000064ffffffff000000810000000300000002000001000000000100000003000000000000000100000003 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000110000000020000000000000000000000000200000064ffffffff000000810000000300000002000001100000000100000003000000000000000100000003 true - Filter - Behavioral (/home/epilef/Proyectos/FiltroHDL/FiltroHDL/Filter.vhd) + Filter - Behavioral (/home/epilef/4-FiltroHDL/FiltroHDL/Filter.vhd) @@ -40,7 +40,7 @@ 0 0 - 000000ff000000000000000100000000000000000100000000000000000000000000000000000005a4000000040101000100000000000000000000000064ffffffff0000008100000000000000040000009f0000000100000000000000280000000100000000000000790000000100000000000004640000000100000000 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000284000000040101000100000000000000000000000064ffffffff0000008100000000000000040000009f0000000100000000000000280000000100000000000000790000000100000000000001440000000100000000 false Filter.vhd @@ -52,7 +52,7 @@ 0 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000125000000010001000100000000000000000000000064ffffffff000000810000000000000001000001250000000100000000 false work @@ -70,13 +70,13 @@ User Constraints - + Synthesize - XST 0 0 - 000000ff000000000000000100000001000000000000000000000000000000000000000000000000e1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e10000000100000000 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000198000000010000000100000000000000000000000064ffffffff000000810000000000000001000001980000000100000000 false - + Synthesize - XST 000000ff00000000000000020000013f0000012001000000060100000002 Implementation @@ -127,12 +127,12 @@ User Constraints - + 0 0 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000 false - + diff --git a/FiltroTestM/.gitignore b/FiltroTestM/.gitignore new file mode 100644 index 0000000..f8644c1 --- /dev/null +++ b/FiltroTestM/.gitignore @@ -0,0 +1,3 @@ +*.htm +*.log +*.autosave diff --git a/FiltroTestM/FilterWrapper_config.m b/FiltroTestM/FilterWrapper_config.m index 5badc8e..98d6079 100644 --- a/FiltroTestM/FilterWrapper_config.m +++ b/FiltroTestM/FilterWrapper_config.m @@ -21,10 +21,17 @@ function FilterWrapper_config(this_block) this_block.addSimulinkOutport('d_o'); + this_block.addSimulinkOutport('p_o'); + + d_o_port = this_block.port('d_o'); d_o_port.setType('UFix_1_0'); d_o_port.useHDLVector(false); + p_o_port = this_block.port('p_o'); + p_o_port.setType('UFix_10_0'); + p_o_port.useHDLVector(true); + % ----------------------------- if (this_block.inputTypesKnown) % do input type checking, dynamic output type and generic setup in this code block. @@ -52,9 +59,12 @@ function FilterWrapper_config(this_block) % on input types, make the settings in the "inputTypesKnown" code block. % The addGeneric function takes 3 parameters, generic name, type and constant value. % Supported types are boolean, real, integer and string. - this_block.addGeneric('CLK_FREQ','integer','1000'); + this_block.addGeneric('CLK_FREQ','integer','500'); this_block.addGeneric('DATA_RATE','integer','1'); this_block.addGeneric('SIMETRIC','boolean','TRUE'); + this_block.addGeneric('CONSTANTS','array_of_integers','(-6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7)'); + + % Add addtional source files as needed. % |------------- @@ -69,7 +79,7 @@ function FilterWrapper_config(this_block) % this_block.addFile(''); % this_block.addFile(''); - this_block.addFile('../FiltroHDL/array_functions.vhd'); + this_block.addFile('../FiltroHDL/filter_pkg.vhd'); this_block.addFile('../FiltroHDL/Filter.vhd'); this_block.addFile('../FiltroHDL/FilterWrapper.vhd'); diff --git a/FiltroTestM/TestModel.mdl b/FiltroTestM/TestModel.mdl index 6b2f087..7c9e961 100644 --- a/FiltroTestM/TestModel.mdl +++ b/FiltroTestM/TestModel.mdl @@ -1,16 +1,17 @@ Model { Name "TestModel" - Version 8.5 + Version 7.9 MdlSubVersion 0 - SavedCharacterEncoding "US-ASCII" GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" - ComputedModelVersion "1.40" + ComputedModelVersion "1.62" NumModelReferences 0 NumTestPointedSignals 0 } + SavedCharacterEncoding "US-ASCII" + SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes on @@ -20,54 +21,15 @@ Model { MinMaxOverflowArchiveMode "Overwrite" FPTRunName "Run 1" MaxMDLFileLineLength 120 - Object { - $PropName "BdWindowsInfo" - $ObjectID 1 - $ClassName "Simulink.BDWindowsInfo" - Object { - $PropName "WindowsInfo" - $ObjectID 2 - $ClassName "Simulink.WindowInfo" - IsActive [1] - Location [0.0, 26.0, 1215.0, 795.0] - Object { - $PropName "ModelBrowserInfo" - $ObjectID 3 - $ClassName "Simulink.ModelBrowserInfo" - Visible [0] - DockPosition "Left" - Width [50] - Height [50] - Filter [9] - } - Object { - $PropName "ExplorerBarInfo" - $ObjectID 4 - $ClassName "Simulink.ExplorerBarInfo" - Visible [1] - } - Object { - $PropName "EditorsInfo" - $ObjectID 5 - $ClassName "Simulink.EditorInfo" - IsActive [1] - ViewObjType "SimulinkTopLevel" - LoadSaveID "0" - Extents [1167.0, 630.0] - ZoomFactor [1.0] - Offset [61.965780646440635, -33.46793720370988] - } - } - } Created "Mon Mar 06 15:39:53 2017" Creator "epilef" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "epilef" ModifiedDateFormat "%" - LastModifiedDate "Mon Mar 06 20:22:18 2017" - RTWModifiedTimeStamp 410732514 - ModelVersionFormat "1.%" + LastModifiedDate "Wed Mar 08 13:52:04 2017" + RTWModifiedTimeStamp 410871668 + ModelVersionFormat "1.%" ConfigurationManager "none" SampleTimeColors off SampleTimeAnnotations off @@ -85,7 +47,6 @@ Model { SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on - ShowMarkup on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off @@ -94,11 +55,6 @@ Model { BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" - PauseTimes "5" - NumberOfSteps 1 - SnapshotBufferSize 10 - SnapshotInterval 10 - NumberOfLastSnapshots 0 LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" @@ -108,9 +64,10 @@ Model { TryForcingSFcnDF off Object { $PropName "DataLoggingOverride" - $ObjectID 6 + $ObjectID 1 $ClassName "Simulink.SimulationData.ModelLoggingInfo" model_ "TestModel" + signals_ [] overrideMode_ [0.0] Array { Type "Cell" @@ -132,7 +89,6 @@ Model { CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on - CovEnableCumulative on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" @@ -140,12 +96,6 @@ Model { CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off - CovSFcnEnable on - CovBoundaryAbsTol 0.000010 - CovBoundaryRelTol 0.010000 - CovUseTimeInterval off - CovStartTime 0 - CovStopTime 0 ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" @@ -167,20 +117,21 @@ Model { ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on + BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { - $ObjectID 7 - Version "1.15.0" + $ObjectID 2 + Version "1.12.0" Array { Type "Handle" Dimension 9 Simulink.SolverCC { - $ObjectID 8 - Version "1.15.0" + $ObjectID 3 + Version "1.12.0" StartTime "0.0" StopTime "5000" AbsTol "auto" @@ -214,8 +165,8 @@ Model { InsertRTBMode "Whenever possible" } Simulink.DataIOCC { - $ObjectID 9 - Version "1.15.0" + $ObjectID 4 + Version "1.12.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" @@ -233,7 +184,6 @@ Model { SignalLogging on DSMLogging on InspectSignalLogs off - VisualizeSimOutput on SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" @@ -247,8 +197,8 @@ Model { Refine "1" } Simulink.OptimizationCC { - $ObjectID 10 - Version "1.15.0" + $ObjectID 5 + Version "1.12.0" Array { Type "Cell" Dimension 8 @@ -266,16 +216,13 @@ Model { BooleanDataType on ConditionallyExecuteInputs on InlineParams off - UseDivisionForNetSlopeComputation "off" + UseIntDivNetSlope off UseFloatMulNetSlope off - DefaultUnderspecifiedDataType "double" UseSpecifiedMinMax off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off - CachingGlobalReferences off - GlobalBufferReuse on StrengthReduction off ExpressionFolding on BooleansAsBitfields off @@ -283,13 +230,14 @@ Model { EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" - PassReuseOutputArgsThreshold 12 ExpressionDepthLimit 128 + FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 + SystemCodeInlineAuto off StateBitsets off DataBitsets off - ActiveStateOutputEnumStorageType "Native Integer" + UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero off @@ -300,12 +248,13 @@ Model { LifeSpan "inf" MaxStackSize "Inherit from target" BufferReusableBoundary on - SimCompilerOptimization "off" + SimCompilerOptimization "Off" AccelVerboseBuild off + ParallelExecutionInRapidAccelerator on } Simulink.DebuggingCC { - $ObjectID 11 - Version "1.15.0" + $ObjectID 6 + Version "1.12.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" @@ -354,7 +303,7 @@ Model { UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" - FcnCallInpInsideContextMsg "EnableAllAsError" + FcnCallInpInsideContextMsg "Enable All" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" @@ -365,10 +314,12 @@ Model { BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" + EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" + ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" @@ -380,6 +331,7 @@ Model { StrictBusMsg "ErrorLevel1" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" + LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" @@ -387,19 +339,14 @@ Model { SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" SFUnconditionalTransitionShadowingDiag "warning" - SFUndirectedBroadcastEventsDiag "warning" - SFTransitionActionBeforeConditionDiag "warning" - SFOutputUsedAsStateInMooreChartDiag "error" - IntegerSaturationMsg "warning" } Simulink.HardwareCC { - $ObjectID 12 - Version "1.15.0" + $ObjectID 7 + Version "1.12.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 - ProdBitPerLongLong 64 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 @@ -409,23 +356,21 @@ Model { ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on - ProdLongLongMode off ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 - TargetBitPerLongLong 64 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on - TargetLongLongMode off TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 + TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" @@ -433,8 +378,8 @@ Model { ProdEqTarget on } Simulink.ModelReferenceCC { - $ObjectID 13 - Version "1.15.0" + $ObjectID 8 + Version "1.12.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off @@ -448,21 +393,23 @@ Model { SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { - $ObjectID 14 - Version "1.15.0" + $ObjectID 9 + Version "1.12.0" + SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on + SimBlas on SimCtrlC on + SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" - SimGenImportedTypeDefs off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" - $ObjectID 15 - Version "1.15.0" + $ObjectID 10 + Version "1.12.0" Array { Type "Cell" Dimension 16 @@ -485,15 +432,10 @@ Model { PropName "DisabledProps" } SystemTargetFile "grt.tlc" - TLCOptions "" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on - PackageGeneratedCodeAndArtifacts off - PackageName "" TemplateMakefile "grt_default_tmf" - PostCodeGenCommand "" - Description "" GenerateReport off SaveLog off RTWVerbose on @@ -502,47 +444,34 @@ Model { TLCDebug off TLCCoverage off TLCAssert off + ProcessScriptMode "Default" + ConfigurationMode "Optimized" + ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off - CustomSourceCode "" - CustomHeaderCode "" - CustomInclude "" - CustomSource "" - CustomLibrary "" - CustomInitializer "" - CustomTerminator "" - Toolchain "Automatically locate an installed toolchain" - BuildConfiguration "Faster Builds" IncludeHyperlinkInReport off LaunchReport off - PortableWordSizes off - CreateSILPILBlock "None" - CodeExecutionProfiling off - CodeExecutionProfileVariable "executionProfile" - CodeProfilingSaveOptions "SummaryOnly" - CodeProfilingInstrumentation off - SILDebugging off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off + IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off + GenerateCodeInfo off GenerateWebview off GenerateCodeMetricsReport off GenerateCodeReplacementReport off - GenerateMissedCodeReplacementReport off - RTWCompilerOptimization "off" - RTWCustomCompilerOptimizations "" + RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" - SharedConstantsCachingThreshold 1024 + CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { - $ObjectID 16 - Version "1.15.0" + $ObjectID 11 + Version "1.12.0" Array { Type "Cell" Dimension 24 @@ -574,7 +503,6 @@ Model { } ForceParamTrailComments off GenerateComments on - CommentStyle "Auto" IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off @@ -582,7 +510,6 @@ Model { PreserveName off PreserveNameWithParent off ShowEliminatedStatement off - OperatorAnnotations off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off @@ -597,7 +524,6 @@ Model { CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" - CustomSymbolStrUtil "$N$C" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" @@ -606,15 +532,14 @@ Model { SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off - InternalIdentifier "Shortened" InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" - $ObjectID 17 - Version "1.15.0" + $ObjectID 12 + Version "1.12.0" Array { Type "Cell" Dimension 13 @@ -636,17 +561,16 @@ Model { TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" - GenFloatMathFcnCalls "NOT IN USE" - TargetLangStandard "C89/C90 (ANSI)" CodeReplacementLibrary "None" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" + CodeExecutionProfiling off ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on - InferredTypesCompatibility off GenerateSampleERTMain off GenerateTestInterfaces off + IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on @@ -663,22 +587,19 @@ Model { LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off - CodeInterfacePackaging "Nonreusable function" SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off + EnableShiftOperators on ParenthesesLevel "Nominal" - CastingMode "Nominal" - MATLABClassNameForMDSCustomization "Simulink.SoftwareTarget.GRTCustomization" + PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant on AutosarCompliant off GRTInterface off - GenerateAllocFcn off - GenerateSharedConstants on UseMalloc off ExtMode off ExtModeStaticAlloc off @@ -692,14 +613,13 @@ Model { RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off - MultiInstanceErrorCode "Error" } PropName "Components" } } hdlcoderui.hdlcc { - $ObjectID 18 - Version "1.15.0" + $ObjectID 13 + Version "1.12.0" Description "HDL Coder custom configuration component" Name "HDL Coder" Array { @@ -720,17 +640,7 @@ Model { } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" - $ObjectID 7 - } - Object { - $PropName "DataTransfer" - $ObjectID 19 - $ClassName "Simulink.GlobalDataTransfer" - DefaultTransitionBetweenSyncTasks "Ensure deterministic transfer (maximum delay)" - DefaultTransitionBetweenAsyncTasks "Ensure data integrity only" - DefaultTransitionBetweenContTasks "Ensure deterministic transfer (minimum delay)" - DefaultExtrapolationMethodBetweenContTasks "None" - AutoInsertRateTranBlk [0] + $ObjectID 2 } ExplicitPartitioning off BlockDefaults { @@ -764,25 +674,6 @@ Model { FontWeight "normal" FontAngle "normal" } - MaskDefaults { - SelfModifiable "off" - IconFrame "on" - IconOpaque "on" - RunInitForIconRedraw "off" - IconRotate "none" - PortRotate "default" - IconUnits "autoscale" - } - MaskParameterDefaults { - Evaluate "on" - Tunable "on" - NeverSave "off" - Internal "off" - ReadOnly "off" - Enabled "on" - Visible "on" - ToolTip "on" - } BlockParameterDefaults { Block { BlockType DiscretePulseGenerator @@ -801,7 +692,6 @@ Model { TickLabels "OneTimeTick" ZoomMode "on" Grid "on" - ShowLegends off TimeRange "auto" YMin "-5" YMax "5" @@ -813,7 +703,6 @@ Model { Decimation "1" SampleInput off SampleTime "-1" - ScrollMode off } Block { BlockType Sum @@ -834,7 +723,7 @@ Model { } System { Name "TestModel" - Location [0, 26, 1215, 821] + Location [6, 56, 1221, 761] Open on ModelBrowserVisibility off ModelBrowserWidth 200 @@ -848,14 +737,14 @@ Model { ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" - SIDHighWatermark "19" + SIDHighWatermark "23" Block { BlockType Reference Name " System Generator" SID "6" Tag "genX" Ports [] - Position [317, 27, 367, 77] + Position [147, 32, 197, 82] ZOrder 139 ShowName off AttributesFormatString "System\\nGenerator" @@ -864,7 +753,6 @@ Model { UserData "DataTag0" SourceBlock "xbsIndex_r4/ System Generator" SourceType "Xilinx System Generator Block" - ContentPreviewEnabled off infoedit " System Generator" xilinxfamily "spartan6" part "xc6slx25" @@ -904,9 +792,9 @@ Model { Name "Aumento del Risetime" SID "7" Ports [1, 1] - Position [355, 167, 420, 223] + Position [185, 172, 250, 228] ZOrder 143 - LibraryVersion "1.332" + LibraryVersion "1.320" SourceBlock "dsparch4/Analog\nFilter Design" SourceType "Analog Filter Design" method "Butterworth" @@ -916,13 +804,57 @@ Model { Whi "80" Rp "2" Rs "40" + Port { + PortNumber 1 + Name "Limitada en BW" + RTWStorageClass "Auto" + DataLoggingNameMode "SignalName" + } + } + Block { + BlockType Reference + Name "Convert" + SID "22" + Ports [1, 1] + Position [615, 205, 660, 235] + LibraryVersion "1.2" + SourceBlock "xbsIndex_r4/Convert" + SourceType "Xilinx Type Converter Block" + infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do " + "not." + gui_display_data_type "Fixed-point" + arith_type "Signed (2's comp)" + n_bits "10" + bin_pt "0" + float_type "Single" + exp_bits "8" + fraction_bits "24" + quantization "Truncate" + overflow "Wrap" + en off + latency "0" + dbl_ovrd off + pipeline off + xl_use_area off + xl_area "[0,0,0,0,0,0,0]" + has_advanced_control "0" + sggui_pos "20,21,519,624" + block_type "convert" + sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" + sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0." + "82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 " + "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 1" + "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1" + " ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.97" + "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port" + "_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Filtro" SID "5" - Ports [1, 1] - Position [700, 167, 755, 223] + Ports [1, 2] + Position [530, 154, 590, 241] ZOrder 5 LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Black Box" @@ -938,24 +870,24 @@ Model { xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" - sggui_pos "-1,-1,-1,-1" + sggui_pos "20,21,419,454" block_type "blackbox2" - sg_icon_stat "55,56,1,1,white,blue,0,5474a0b4,right,,[ ],[ ]" - sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0." - "82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[" - "35.77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 2" - "8.77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28" - ".77 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21." - "77 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" - "xt');\ncolor('black');port_label('input',1,'d_i');\ncolor('black');port_label('output',1,'d_o');\nfprintf('','CO" - "MMENT: end icon text');" + sg_icon_stat "60,87,1,2,white,blue,0,15bc2c65,right,,[ ],[ ]" + sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 87 87 0 ],[0.77 0." + "82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 87 87 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[51.88 " + "51.88 59.88 51.88 59.88 59.88 59.88 51.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[43.88 43.88 51.88 5" + "1.88 43.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[35.88 35.88 43.88 43.88 35.88 ],[1 1 1" + " ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[27.88 27.88 35.88 27.88 35.88 35.88 27.88 ],[0.931 0.946 " + "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" + "rt_label('input',1,'d_i');\ncolor('black');port_label('output',1,'d_o');\ncolor('black');port_label('output',2,'" + "p_o');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway In" SID "15" Ports [1, 1] - Position [575, 185, 640, 205] + Position [405, 190, 470, 210] ZOrder 148 LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" @@ -986,29 +918,28 @@ Model { has_advanced_control "0" sggui_pos "20,26,404,607" block_type "gatewayin" - sg_icon_stat "65,20,1,1,white,yellow,1,e514e594,right,,[ ],[ ]" + sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0." "93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12." "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 1" "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ]," "[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97" "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" - "port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('red');port_label('output',1,' (!) ');" - "\nfprintf('','COMMENT: end icon text');" + "port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfp" + "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gaussian Noise\nGenerator" SID "8" Ports [0, 1] - Position [345, 268, 425, 312] + Position [175, 273, 255, 317] ZOrder 142 - LibraryVersion "1.75" + LibraryVersion "1.74" SourceBlock "commnoisgen2/Gaussian Noise\nGenerator" SourceType "Gaussian Noise Generator" - ContentPreviewEnabled off m "0" - d "1.5" + d "0.1" s "123" Ts "0.1" frameBased off @@ -1020,13 +951,48 @@ Model { BlockType Scope Name "Scope" SID "19" - Ports [3] - Position [990, 73, 1070, 217] + Ports [4] + Position [825, 65, 910, 240] ZOrder 151 Floating off - Location [122, 140, 1402, 968] - Open on + Location [75, 57, 1355, 760] + Open off + NumInputPorts "4" + ZoomMode "xonly" + List { + ListType AxesTitles + axes1 "%" + axes2 "%" + axes3 "%" + axes4 "%" + } + List { + ListType ScopeGraphics + FigureColor "[0.5 0.5 0.5]" + AxesColor "[0 0 0]" + AxesTickColor "[1 1 1]" + LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" + LineStyles "-|-|-|-|-|-" + LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" + MarkerStyles "none|none|none|none|none|none" + } + ShowLegends off + YMin "-3~-0.1~-0.1~-50" + YMax "4~1.1~1.1~50" + LimitDataPoints off + } + Block { + BlockType Scope + Name "Scope1" + SID "23" + Ports [3] + Position [440, 363, 515, 457] + ZOrder 151 + Floating off + Location [75, 57, 1355, 760] + Open off NumInputPorts "3" + ZoomMode "xonly" List { ListType AxesTitles axes1 "%" @@ -1043,8 +1009,10 @@ Model { LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } + ShowLegends off YMin "-3~-0.1~-0.1" YMax "4~1.1~1.1" + SaveName "ScopeData1" LimitDataPoints off } Block { @@ -1052,11 +1020,11 @@ Model { Name "Senal Original\n" SID "10" Ports [0, 1] - Position [250, 179, 280, 211] + Position [80, 184, 110, 216] ZOrder 140 NamePlacement "alternate" PulseType "Time based" - Period "1000" + Period "500" PulseWidth "50" Port { PortNumber 1 @@ -1065,12 +1033,53 @@ Model { DataLoggingNameMode "SignalName" } } + Block { + BlockType Reference + Name "Senial Interna" + SID "20" + Ports [1, 1] + Position [690, 210, 750, 230] + ZOrder 147 + LibraryVersion "1.2" + SourceBlock "xbsIndex_r4/Gateway Out" + SourceType "Xilinx Gateway Out Block" + infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty" + "pe Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top" + " level output ports or are discarded, depending on how they are configured." + inherit_from_input off + hdl_port on + timing_constraint "None" + locs_specified off + LOCs "{}" + UseAsDAC off + DACChannel "'1'" + xl_use_area off + xl_area "[0,0,0,0,0,0,0]" + has_advanced_control "0" + sggui_pos "20,26,403,629" + block_type "gatewayout" + sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" + sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0." + "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12." + "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1" + "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ]," + "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97" + "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" + "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf" + "printf('','COMMENT: end icon text');" + Port { + PortNumber 1 + Name "Interna" + RTWStorageClass "Auto" + DataLoggingNameMode "SignalName" + } + } Block { BlockType Reference Name "Senial Regenerada\n" SID "14" Ports [1, 1] - Position [790, 185, 850, 205] + Position [690, 165, 750, 185] ZOrder 147 LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" @@ -1099,13 +1108,60 @@ Model { "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" + Port { + PortNumber 1 + Name "Regenerada" + RTWStorageClass "Auto" + DataLoggingNameMode "SignalName" + } + } + Block { + BlockType Reference + Name "Senial Ruidosa" + SID "21" + Ports [1, 1] + Position [690, 120, 750, 140] + ZOrder 147 + LibraryVersion "1.2" + SourceBlock "xbsIndex_r4/Gateway Out" + SourceType "Xilinx Gateway Out Block" + infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty" + "pe Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top" + " level output ports or are discarded, depending on how they are configured." + inherit_from_input off + hdl_port on + timing_constraint "None" + locs_specified off + LOCs "{}" + UseAsDAC off + DACChannel "'1'" + xl_use_area off + xl_area "[0,0,0,0,0,0,0]" + has_advanced_control "0" + sggui_pos "20,26,403,629" + block_type "gatewayout" + sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" + sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0." + "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12." + "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1" + "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ]," + "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97" + "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" + "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf" + "printf('','COMMENT: end icon text');" + Port { + PortNumber 1 + Name "Ruido Digital" + RTWStorageClass "Auto" + DataLoggingNameMode "SignalName" + } } Block { BlockType Sum Name "Sum" SID "13" Ports [2, 1] - Position [465, 185, 485, 205] + Position [295, 190, 315, 210] ZOrder 141 ShowName off IconShape "round" @@ -1121,7 +1177,6 @@ Model { } } Line { - ZOrder 4 SrcBlock "Gaussian Noise\nGenerator" SrcPort 1 Points [45, 0] @@ -1130,57 +1185,60 @@ Model { } Line { Name "Original" - ZOrder 9 Labels [0, 0] SrcBlock "Senal Original\n" SrcPort 1 Points [30, 0] Branch { - ZOrder 57 - Points [0, -50] - DstBlock "Scope" - DstPort 2 - } - Branch { - ZOrder 56 Labels [-1, 0] DstBlock "Aumento del Risetime" DstPort 1 } + Branch { + Points [0, 240] + DstBlock "Scope1" + DstPort 3 + } } Line { - ZOrder 12 + Name "Limitada en BW" + Labels [0, 0] SrcBlock "Aumento del Risetime" SrcPort 1 - DstBlock "Sum" - DstPort 1 + Points [20, 0] + Branch { + DstBlock "Sum" + DstPort 1 + } + Branch { + Points [0, 210] + DstBlock "Scope1" + DstPort 2 + } } Line { - ZOrder 17 SrcBlock "Filtro" SrcPort 1 DstBlock "Senial Regenerada\n" DstPort 1 } Line { - ZOrder 18 SrcBlock "Gateway In" SrcPort 1 Points [23, 0] Branch { - ZOrder 59 - Points [0, -100] - DstBlock "Scope" + DstBlock "Filtro" DstPort 1 } Branch { - ZOrder 58 - DstBlock "Filtro" + Points [0, -70] + DstBlock "Senial Ruidosa" DstPort 1 } } Line { - ZOrder 35 + Name "Regenerada" + Labels [0, 0] SrcBlock "Senial Regenerada\n" SrcPort 1 DstBlock "Scope" @@ -1188,11 +1246,51 @@ Model { } Line { Name "Senal con ruido" - ZOrder 40 Labels [0, 0] SrcBlock "Sum" SrcPort 1 - DstBlock "Gateway In" + Points [30, 0] + Branch { + DstBlock "Gateway In" + DstPort 1 + } + Branch { + Points [0, -115] + DstBlock "Scope" + DstPort 1 + } + Branch { + Points [0, 180] + DstBlock "Scope1" + DstPort 1 + } + } + Line { + SrcBlock "Filtro" + SrcPort 2 + DstBlock "Convert" + DstPort 1 + } + Line { + Name "Interna" + Labels [0, 0] + SrcBlock "Senial Interna" + SrcPort 1 + DstBlock "Scope" + DstPort 4 + } + Line { + Name "Ruido Digital" + Labels [0, 0] + SrcBlock "Senial Ruidosa" + SrcPort 1 + DstBlock "Scope" + DstPort 2 + } + Line { + SrcBlock "Convert" + SrcPort 1 + DstBlock "Senial Interna" DstPort 1 } }