library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


use work.filter_pkg.all;



entity FilterWrapper is
	generic (
		CLK_FREQ : integer  := 50e6;
		DATA_RATE: integer  := 250e3;
		SIMETRIC : boolean := TRUE;
		CONSTANTS : array_of_integers := (-4,-3,-2,-1,0,1,2,3,4,5)
			
	);
	port (
		clk : in std_logic;
		ce: in std_logic;
		
		d_i  : in std_logic;
		d_o  : out std_logic;
		p_o  : out std_logic_vector(9 downto 0)
	);
end FilterWrapper;

architecture Behavioral of FilterWrapper is

begin

   uut: Filter Generic Map(
		CLK_FREQ  => CLK_FREQ,
		DATA_RATE => DATA_RATE,
		SIMETRIC  => SIMETRIC,
		CONSTANTS => CONSTANTS
   )
   PORT MAP (
          clk_i => clk,
          enable => ce,
          reset => '0',
          d_i => d_i,
          d_o => d_o,
	  p_o => p_o
        );



end Behavioral;