--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:47:13 03/03/2017
-- Design Name:   
-- Module Name:   /home/epilef/Proyectos/FiltroHDL/FiltroHDL/Filter_tb.vhd
-- Project Name:  FiltroHDL
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Filter
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

use work.array_functions.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Filter_tb IS
END Filter_tb;
 
ARCHITECTURE behavior OF Filter_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Filter
    generic (
		CLK_FREQ : integer  := 200e6;
		DATA_RATE: integer  := 250e3;


		SIMETRIC : boolean := true;
		CONSTANTS : array_of_integers := (-10,-10,-10,-10,10,10,10,10)
		
	);
    PORT(
         clk_i : IN  std_logic;
         enable : IN  std_logic;
         reset : IN  std_logic;
         d_i : IN  std_logic;
         d_o : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk_i : std_logic := '0';
   signal enable : std_logic := '1';
   signal reset : std_logic := '0';
   signal d_i : std_logic := '0';

 	--Outputs
   signal d_o : std_logic;

   -- Clock period definitions
   constant clk_i_period : time := 5 ns;
   constant data_period : time := 4 us;
   
   
   constant data: std_logic_vector := x"EB901234ABCD5678EF09";
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Filter Generic Map(
		CLK_FREQ  => 200e6,
		DATA_RATE => 250e3,
		SIMETRIC  => true,
		CONSTANTS => ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
   )
   PORT MAP (
          clk_i => clk_i,
          enable => enable,
          reset => reset,
          d_i => d_i,
          d_o => d_o
        );

   -- Clock process definitions
   clk_i_process :process
   begin
		clk_i <= '0';
		wait for clk_i_period/2;
		clk_i <= '1';
		wait for clk_i_period/2;
   end process;
 
	

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

		for i in 0 to data'length -1 loop
			d_i <= data(i);
			wait for data_period;
		end loop;
      -- insert stimulus here 

      wait;
   end process;

END;