function FilterWrapper_config(this_block)

  % Revision History:
  %
  %   06-Mar-2017  (15:49 hours):
  %     Original code was machine generated by Xilinx's System Generator after parsing
  %     /home/epilef/Proyectos/FiltroHDL/FiltroHDL/FilterWrapper.vhd
  %
  %

  this_block.setTopLevelLanguage('VHDL');

  this_block.setEntityName('FilterWrapper');

  % System Generator has to assume that your entity  has a combinational feed through; 
  %   if it  doesn't, then comment out the following line:
  this_block.tagAsCombinational;

  this_block.addSimulinkInport('d_i');

  this_block.addSimulinkOutport('d_o');

  this_block.addSimulinkOutport('p_o');


  d_o_port = this_block.port('d_o');
  d_o_port.setType('UFix_1_0');
  d_o_port.useHDLVector(false);

  p_o_port = this_block.port('p_o');
  p_o_port.setType('UFix_10_0');
  p_o_port.useHDLVector(true);

  % -----------------------------
  if (this_block.inputTypesKnown)
    % do input type checking, dynamic output type and generic setup in this code block.

    if (this_block.port('d_i').width ~= 1);
      this_block.setError('Input data type for port "d_i" must have width=1.');
    end

    this_block.port('d_i').useHDLVector(false);

  end  % if(inputTypesKnown)
  % -----------------------------

  % -----------------------------
   if (this_block.inputRatesKnown)
     setup_as_single_rate(this_block,'clk','ce')
   end  % if(inputRatesKnown)
  % -----------------------------

    % (!) Set the inout port rate to be the same as the first input 
    %     rate. Change the following code if this is untrue.
    uniqueInputRates = unique(this_block.getInputRates);

  % (!) Custimize the following generic settings as appropriate. If any settings depend
  %      on input types, make the settings in the "inputTypesKnown" code block.
  %      The addGeneric function takes  3 parameters, generic name, type and constant value.
  %      Supported types are boolean, real, integer and string.
  this_block.addGeneric('CLK_FREQ','integer','500');
  this_block.addGeneric('DATA_RATE','integer','1');
  this_block.addGeneric('SIMETRIC','boolean','TRUE');
  this_block.addGeneric('CONSTANTS','array_of_integers','(-6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7)');
  
  

  % Add addtional source files as needed.
  %  |-------------
  %  | Add files in the order in which they should be compiled.
  %  | If two files "a.vhd" and "b.vhd" contain the entities
  %  | entity_a and entity_b, and entity_a contains a
  %  | component of type entity_b, the correct sequence of
  %  | addFile() calls would be:
  %  |    this_block.addFile('b.vhd');
  %  |    this_block.addFile('a.vhd');
  %  |-------------

  %    this_block.addFile('');
  %    this_block.addFile('');
  this_block.addFile('../FiltroHDL/filter_pkg.vhd');
  this_block.addFile('../FiltroHDL/Filter.vhd');
  this_block.addFile('../FiltroHDL/FilterWrapper.vhd');
  
return;


% ------------------------------------------------------------

function setup_as_single_rate(block,clkname,cename) 
  inputRates = block.inputRates; 
  uniqueInputRates = unique(inputRates); 
  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
    block.addError('The inputs to this block cannot all be constant.'); 
    return; 
  end 
  if (uniqueInputRates(end) == Inf) 
     hasConstantInput = true; 
     uniqueInputRates = uniqueInputRates(1:end-1); 
  end 
  if (length(uniqueInputRates) ~= 1) 
    block.addError('The inputs to this block must run at a single rate.'); 
    return; 
  end 
  theInputRate = uniqueInputRates(1); 
  for i = 1:block.numSimulinkOutports 
     block.outport(i).setRate(theInputRate); 
  end 
  block.addClkCEPair(clkname,cename,theInputRate); 
  return; 

% ------------------------------------------------------------