Model {
  Name			  "TestModel"
  Version		  7.9
  MdlSubVersion		  0
  GraphicalInterface {
    NumRootInports	    0
    NumRootOutports	    0
    ParameterArgumentNames  ""
    ComputedModelVersion    "1.62"
    NumModelReferences	    0
    NumTestPointedSignals   0
  }
  SavedCharacterEncoding  "US-ASCII"
  SaveDefaultBlockParams  on
  ScopeRefreshTime	  0.035000
  OverrideScopeRefreshTime on
  DisableAllScopes	  on
  DataTypeOverride	  "UseLocalSettings"
  DataTypeOverrideAppliesTo "AllNumericTypes"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  FPTRunName		  "Run 1"
  MaxMDLFileLineLength	  120
  Created		  "Mon Mar 06 15:39:53 2017"
  Creator		  "epilef"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "epilef"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Wed Mar 08 13:52:04 2017"
  RTWModifiedTimeStamp	  410871668
  ModelVersionFormat	  "1.%<AutoIncrement:62>"
  ConfigurationManager	  "none"
  SampleTimeColors	  off
  SampleTimeAnnotations	  off
  LibraryLinkDisplay	  "disabled"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowDesignRanges	  off
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ShowTestPointIcons	  on
  ShowSignalResolutionIcons on
  ShowViewerIcons	  on
  SortedOrder		  off
  ExecutionContextIcon	  off
  ShowLinearizationAnnotations on
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  SimulationMode	  "normal"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  Object {
    $PropName		    "DataLoggingOverride"
    $ObjectID		    1
    $ClassName		    "Simulink.SimulationData.ModelLoggingInfo"
    model_		    "TestModel"
    signals_		    []
    overrideMode_	    [0.0]
    Array {
      Type		      "Cell"
      Dimension		      1
      Cell		      "TestModel"
      PropName		      "logAsSpecifiedByModels_"
    }
    Array {
      Type		      "Cell"
      Dimension		      1
      Cell		      []
      PropName		      "logAsSpecifiedByModelsSSIDs_"
    }
  }
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  CovForceBlockReductionOff on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  CovReportOnPause	  on
  CovModelRefEnable	  "Off"
  CovExternalEMLEnable	  off
  ExtModeBatchMode	  off
  ExtModeEnableFloating	  on
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigDurationFloating "auto"
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  ShowModelReferenceBlockVersion off
  ShowModelReferenceBlockIO off
  Array {
    Type		    "Handle"
    Dimension		    1
    Simulink.ConfigSet {
      $ObjectID		      2
      Version		      "1.12.0"
      Array {
	Type			"Handle"
	Dimension		9
	Simulink.SolverCC {
	  $ObjectID		  3
	  Version		  "1.12.0"
	  StartTime		  "0.0"
	  StopTime		  "5000"
	  AbsTol		  "auto"
	  FixedStep		  "auto"
	  InitialStep		  "auto"
	  MaxNumMinSteps	  "-1"
	  MaxOrder		  5
	  ZcThreshold		  "auto"
	  ConsecutiveZCsStepRelTol "10*128*eps"
	  MaxConsecutiveZCs	  "1000"
	  ExtrapolationOrder	  4
	  NumberNewtonIterations  1
	  MaxStep		  "auto"
	  MinStep		  "auto"
	  MaxConsecutiveMinStep	  "1"
	  RelTol		  "1e-3"
	  SolverMode		  "Auto"
	  EnableConcurrentExecution off
	  ConcurrentTasks	  off
	  Solver		  "ode45"
	  SolverName		  "ode45"
	  SolverJacobianMethodControl "auto"
	  ShapePreserveControl	  "DisableAll"
	  ZeroCrossControl	  "UseLocalSettings"
	  ZeroCrossAlgorithm	  "Nonadaptive"
	  AlgebraicLoopSolver	  "TrustRegion"
	  SolverResetMethod	  "Fast"
	  PositivePriorityOrder	  off
	  AutoInsertRateTranBlk	  off
	  SampleTimeConstraint	  "Unconstrained"
	  InsertRTBMode		  "Whenever possible"
	}
	Simulink.DataIOCC {
	  $ObjectID		  4
	  Version		  "1.12.0"
	  Decimation		  "1"
	  ExternalInput		  "[t, u]"
	  FinalStateName	  "xFinal"
	  InitialState		  "xInitial"
	  LimitDataPoints	  on
	  MaxDataPoints		  "1000"
	  LoadExternalInput	  off
	  LoadInitialState	  off
	  SaveFinalState	  off
	  SaveCompleteFinalSimState off
	  SaveFormat		  "Array"
	  SignalLoggingSaveFormat "Dataset"
	  SaveOutput		  on
	  SaveState		  off
	  SignalLogging		  on
	  DSMLogging		  on
	  InspectSignalLogs	  off
	  SaveTime		  on
	  ReturnWorkspaceOutputs  off
	  StateSaveName		  "xout"
	  TimeSaveName		  "tout"
	  OutputSaveName	  "yout"
	  SignalLoggingName	  "logsout"
	  DSMLoggingName	  "dsmout"
	  OutputOption		  "RefineOutputTimes"
	  OutputTimes		  "[]"
	  ReturnWorkspaceOutputsName "out"
	  Refine		  "1"
	}
	Simulink.OptimizationCC {
	  $ObjectID		  5
	  Version		  "1.12.0"
	  Array {
	    Type		    "Cell"
	    Dimension		    8
	    Cell		    "BooleansAsBitfields"
	    Cell		    "PassReuseOutputArgsAs"
	    Cell		    "PassReuseOutputArgsThreshold"
	    Cell		    "ZeroExternalMemoryAtStartup"
	    Cell		    "ZeroInternalMemoryAtStartup"
	    Cell		    "OptimizeModelRefInitCode"
	    Cell		    "NoFixptDivByZeroProtection"
	    Cell		    "UseSpecifiedMinMax"
	    PropName		    "DisabledProps"
	  }
	  BlockReduction	  on
	  BooleanDataType	  on
	  ConditionallyExecuteInputs on
	  InlineParams		  off
	  UseIntDivNetSlope	  off
	  UseFloatMulNetSlope	  off
	  UseSpecifiedMinMax	  off
	  InlineInvariantSignals  off
	  OptimizeBlockIOStorage  on
	  BufferReuse		  on
	  EnhancedBackFolding	  off
	  StrengthReduction	  off
	  ExpressionFolding	  on
	  BooleansAsBitfields	  off
	  BitfieldContainerType	  "uint_T"
	  EnableMemcpy		  on
	  MemcpyThreshold	  64
	  PassReuseOutputArgsAs	  "Structure reference"
	  ExpressionDepthLimit	  128
	  FoldNonRolledExpr	  on
	  LocalBlockOutputs	  on
	  RollThreshold		  5
	  SystemCodeInlineAuto	  off
	  StateBitsets		  off
	  DataBitsets		  off
	  UseTempVars		  off
	  ZeroExternalMemoryAtStartup on
	  ZeroInternalMemoryAtStartup on
	  InitFltsAndDblsToZero	  off
	  NoFixptDivByZeroProtection off
	  EfficientFloat2IntCast  off
	  EfficientMapNaN2IntZero on
	  OptimizeModelRefInitCode off
	  LifeSpan		  "inf"
	  MaxStackSize		  "Inherit from target"
	  BufferReusableBoundary  on
	  SimCompilerOptimization "Off"
	  AccelVerboseBuild	  off
	  ParallelExecutionInRapidAccelerator on
	}
	Simulink.DebuggingCC {
	  $ObjectID		  6
	  Version		  "1.12.0"
	  RTPrefix		  "error"
	  ConsistencyChecking	  "none"
	  ArrayBoundsChecking	  "none"
	  SignalInfNanChecking	  "none"
	  SignalRangeChecking	  "none"
	  ReadBeforeWriteMsg	  "UseLocalSettings"
	  WriteAfterWriteMsg	  "UseLocalSettings"
	  WriteAfterReadMsg	  "UseLocalSettings"
	  AlgebraicLoopMsg	  "warning"
	  ArtificialAlgebraicLoopMsg "warning"
	  SaveWithDisabledLinksMsg "warning"
	  SaveWithParameterizedLinksMsg	"warning"
	  CheckSSInitialOutputMsg on
	  UnderspecifiedInitializationDetection	"Simplified"
	  MergeDetectMultiDrivingBlocksExec "error"
	  CheckExecutionContextPreStartOutputMsg off
	  CheckExecutionContextRuntimeOutputMsg	off
	  SignalResolutionControl "UseLocalSettings"
	  BlockPriorityViolationMsg "warning"
	  MinStepSizeMsg	  "warning"
	  TimeAdjustmentMsg	  "none"
	  MaxConsecutiveZCsMsg	  "error"
	  MaskedZcDiagnostic	  "warning"
	  IgnoredZcDiagnostic	  "warning"
	  SolverPrmCheckMsg	  "none"
	  InheritedTsInSrcMsg	  "warning"
	  DiscreteInheritContinuousMsg "warning"
	  MultiTaskDSMMsg	  "error"
	  MultiTaskCondExecSysMsg "error"
	  MultiTaskRateTransMsg	  "error"
	  SingleTaskRateTransMsg  "none"
	  TasksWithSamePriorityMsg "warning"
	  SigSpecEnsureSampleTimeMsg "warning"
	  CheckMatrixSingularityMsg "none"
	  IntegerOverflowMsg	  "warning"
	  Int32ToFloatConvMsg	  "warning"
	  ParameterDowncastMsg	  "error"
	  ParameterOverflowMsg	  "error"
	  ParameterUnderflowMsg	  "none"
	  ParameterPrecisionLossMsg "warning"
	  ParameterTunabilityLossMsg "warning"
	  FixptConstUnderflowMsg  "none"
	  FixptConstOverflowMsg	  "none"
	  FixptConstPrecisionLossMsg "none"
	  UnderSpecifiedDataTypeMsg "none"
	  UnnecessaryDatatypeConvMsg "none"
	  VectorMatrixConversionMsg "none"
	  InvalidFcnCallConnMsg	  "error"
	  FcnCallInpInsideContextMsg "Enable All"
	  SignalLabelMismatchMsg  "none"
	  UnconnectedInputMsg	  "warning"
	  UnconnectedOutputMsg	  "warning"
	  UnconnectedLineMsg	  "warning"
	  SFcnCompatibilityMsg	  "none"
	  FrameProcessingCompatibilityMsg "error"
	  UniqueDataStoreMsg	  "none"
	  BusObjectLabelMismatch  "warning"
	  RootOutportRequireBusObject "warning"
	  AssertControl		  "UseLocalSettings"
	  EnableOverflowDetection off
	  ModelReferenceIOMsg	  "none"
	  ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error"
	  ModelReferenceVersionMismatchMessage "none"
	  ModelReferenceIOMismatchMessage "none"
	  ModelReferenceCSMismatchMessage "none"
	  UnknownTsInhSupMsg	  "warning"
	  ModelReferenceDataLoggingMessage "warning"
	  ModelReferenceSymbolNameMessage "warning"
	  ModelReferenceExtraNoncontSigs "error"
	  StateNameClashWarn	  "none"
	  SimStateInterfaceChecksumMismatchMsg "warning"
	  SimStateOlderReleaseMsg "error"
	  InitInArrayFormatMsg	  "warning"
	  StrictBusMsg		  "ErrorLevel1"
	  BusNameAdapt		  "WarnAndRepair"
	  NonBusSignalsTreatedAsBus "none"
	  LoggingUnavailableSignals "error"
	  BlockIODiagnostic	  "none"
	  SFUnusedDataAndEventsDiag "warning"
	  SFUnexpectedBacktrackingDiag "warning"
	  SFInvalidInputDataAccessInChartInitDiag "warning"
	  SFNoUnconditionalDefaultTransitionDiag "warning"
	  SFTransitionOutsideNaturalParentDiag "warning"
	  SFUnconditionalTransitionShadowingDiag "warning"
	}
	Simulink.HardwareCC {
	  $ObjectID		  7
	  Version		  "1.12.0"
	  ProdBitPerChar	  8
	  ProdBitPerShort	  16
	  ProdBitPerInt		  32
	  ProdBitPerLong	  32
	  ProdBitPerFloat	  32
	  ProdBitPerDouble	  64
	  ProdBitPerPointer	  32
	  ProdLargestAtomicInteger "Char"
	  ProdLargestAtomicFloat  "None"
	  ProdIntDivRoundTo	  "Undefined"
	  ProdEndianess		  "Unspecified"
	  ProdWordSize		  32
	  ProdShiftRightIntArith  on
	  ProdHWDeviceType	  "32-bit Generic"
	  TargetBitPerChar	  8
	  TargetBitPerShort	  16
	  TargetBitPerInt	  32
	  TargetBitPerLong	  32
	  TargetBitPerFloat	  32
	  TargetBitPerDouble	  64
	  TargetBitPerPointer	  32
	  TargetLargestAtomicInteger "Char"
	  TargetLargestAtomicFloat "None"
	  TargetShiftRightIntArith on
	  TargetIntDivRoundTo	  "Undefined"
	  TargetEndianess	  "Unspecified"
	  TargetWordSize	  32
	  TargetTypeEmulationWarnSuppressLevel 0
	  TargetPreprocMaxBitsSint 32
	  TargetPreprocMaxBitsUint 32
	  TargetHWDeviceType	  "Specified"
	  TargetUnknown		  off
	  ProdEqTarget		  on
	}
	Simulink.ModelReferenceCC {
	  $ObjectID		  8
	  Version		  "1.12.0"
	  UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
	  CheckModelReferenceTargetMessage "error"
	  EnableParallelModelReferenceBuilds off
	  ParallelModelReferenceErrorOnInvalidPool on
	  ParallelModelReferenceMATLABWorkerInit "None"
	  ModelReferenceNumInstancesAllowed "Multi"
	  PropagateVarSize	  "Infer from blocks in model"
	  ModelReferencePassRootInputsByReference on
	  ModelReferenceMinAlgLoopOccurrences off
	  PropagateSignalLabelsOutOfModel off
	  SupportModelReferenceSimTargetCustomCode off
	}
	Simulink.SFSimCC {
	  $ObjectID		  9
	  Version		  "1.12.0"
	  SFSimEnableDebug	  on
	  SFSimOverflowDetection  on
	  SFSimEcho		  on
	  SimBlas		  on
	  SimCtrlC		  on
	  SimExtrinsic		  on
	  SimIntegrity		  on
	  SimUseLocalCustomCode	  off
	  SimParseCustomCode	  on
	  SimBuildMode		  "sf_incremental_build"
	}
	Simulink.RTWCC {
	  $BackupClass		  "Simulink.RTWCC"
	  $ObjectID		  10
	  Version		  "1.12.0"
	  Array {
	    Type		    "Cell"
	    Dimension		    16
	    Cell		    "IncludeHyperlinkInReport"
	    Cell		    "GenerateTraceInfo"
	    Cell		    "GenerateTraceReport"
	    Cell		    "GenerateTraceReportSl"
	    Cell		    "GenerateTraceReportSf"
	    Cell		    "GenerateTraceReportEml"
	    Cell		    "PortableWordSizes"
	    Cell		    "GenerateWebview"
	    Cell		    "GenerateCodeMetricsReport"
	    Cell		    "GenerateCodeReplacementReport"
	    Cell		    "GenerateMissedCodeReplacementReport"
	    Cell		    "GenerateErtSFunction"
	    Cell		    "CreateSILPILBlock"
	    Cell		    "CodeExecutionProfiling"
	    Cell		    "CodeProfilingSaveOptions"
	    Cell		    "CodeProfilingInstrumentation"
	    PropName		    "DisabledProps"
	  }
	  SystemTargetFile	  "grt.tlc"
	  GenCodeOnly		  off
	  MakeCommand		  "make_rtw"
	  GenerateMakefile	  on
	  TemplateMakefile	  "grt_default_tmf"
	  GenerateReport	  off
	  SaveLog		  off
	  RTWVerbose		  on
	  RetainRTWFile		  off
	  ProfileTLC		  off
	  TLCDebug		  off
	  TLCCoverage		  off
	  TLCAssert		  off
	  ProcessScriptMode	  "Default"
	  ConfigurationMode	  "Optimized"
	  ConfigAtBuild		  off
	  RTWUseLocalCustomCode	  off
	  RTWUseSimCustomCode	  off
	  IncludeHyperlinkInReport off
	  LaunchReport		  off
	  TargetLang		  "C"
	  IncludeBusHierarchyInRTWFileBlockHierarchyMap	off
	  IncludeERTFirstTime	  off
	  GenerateTraceInfo	  off
	  GenerateTraceReport	  off
	  GenerateTraceReportSl	  off
	  GenerateTraceReportSf	  off
	  GenerateTraceReportEml  off
	  GenerateCodeInfo	  off
	  GenerateWebview	  off
	  GenerateCodeMetricsReport off
	  GenerateCodeReplacementReport	off
	  RTWCompilerOptimization "Off"
	  CheckMdlBeforeBuild	  "Off"
	  CustomRebuildMode	  "OnUpdate"
	  Array {
	    Type		    "Handle"
	    Dimension		    2
	    Simulink.CodeAppCC {
	      $ObjectID		      11
	      Version		      "1.12.0"
	      Array {
		Type			"Cell"
		Dimension		24
		Cell			"IgnoreCustomStorageClasses"
		Cell			"ParameterTuningSideEffectCode"
		Cell			"IgnoreTestpoints"
		Cell			"InsertBlockDesc"
		Cell			"InsertPolySpaceComments"
		Cell			"SFDataObjDesc"
		Cell			"MATLABFcnDesc"
		Cell			"SimulinkDataObjDesc"
		Cell			"DefineNamingRule"
		Cell			"SignalNamingRule"
		Cell			"ParamNamingRule"
		Cell			"InternalIdentifier"
		Cell			"InlinedPrmAccess"
		Cell			"CustomSymbolStr"
		Cell			"CustomSymbolStrGlobalVar"
		Cell			"CustomSymbolStrType"
		Cell			"CustomSymbolStrField"
		Cell			"CustomSymbolStrFcn"
		Cell			"CustomSymbolStrFcnArg"
		Cell			"CustomSymbolStrBlkIO"
		Cell			"CustomSymbolStrTmpVar"
		Cell			"CustomSymbolStrMacro"
		Cell			"CustomSymbolStrUtil"
		Cell			"ReqsInCode"
		PropName		"DisabledProps"
	      }
	      ForceParamTrailComments off
	      GenerateComments	      on
	      IgnoreCustomStorageClasses on
	      IgnoreTestpoints	      off
	      IncHierarchyInIds	      off
	      MaxIdLength	      31
	      PreserveName	      off
	      PreserveNameWithParent  off
	      ShowEliminatedStatement off
	      IncAutoGenComments      off
	      SimulinkDataObjDesc     off
	      SFDataObjDesc	      off
	      MATLABFcnDesc	      off
	      IncDataTypeInIds	      off
	      MangleLength	      1
	      CustomSymbolStrGlobalVar "$R$N$M"
	      CustomSymbolStrType     "$N$R$M_T"
	      CustomSymbolStrField    "$N$M"
	      CustomSymbolStrFcn      "$R$N$M$F"
	      CustomSymbolStrFcnArg   "rt$I$N$M"
	      CustomSymbolStrBlkIO    "rtb_$N$M"
	      CustomSymbolStrTmpVar   "$N$M"
	      CustomSymbolStrMacro    "$R$N$M"
	      DefineNamingRule	      "None"
	      ParamNamingRule	      "None"
	      SignalNamingRule	      "None"
	      InsertBlockDesc	      off
	      InsertPolySpaceComments off
	      SimulinkBlockComments   on
	      MATLABSourceComments    off
	      EnableCustomComments    off
	      InlinedPrmAccess	      "Literals"
	      ReqsInCode	      off
	      UseSimReservedNames     off
	    }
	    Simulink.GRTTargetCC {
	      $BackupClass	      "Simulink.TargetCC"
	      $ObjectID		      12
	      Version		      "1.12.0"
	      Array {
		Type			"Cell"
		Dimension		13
		Cell			"GeneratePreprocessorConditionals"
		Cell			"IncludeMdlTerminateFcn"
		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
		Cell			"GenerateTestInterfaces"
		Cell			"ModelStepFunctionPrototypeControlCompliant"
		Cell			"GenerateAllocFcn"
		Cell			"PurelyIntegerCode"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		PropName		"DisabledProps"
	      }
	      TargetFcnLib	      "ansi_tfl_table_tmw.mat"
	      TargetLibSuffix	      ""
	      TargetPreCompLibLocation ""
	      CodeReplacementLibrary  "None"
	      UtilityFuncGeneration   "Auto"
	      ERTMultiwordTypeDef     "System defined"
	      CodeExecutionProfiling  off
	      ERTMultiwordLength      256
	      MultiwordLength	      2048
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      GenerateTestInterfaces  off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      ParMdlRefBuildCompliant on
	      CompOptLevelCompliant   on
	      ConcurrentExecutionCompliant on
	      IncludeMdlTerminateFcn  on
	      GeneratePreprocessorConditionals "Disable all"
	      CombineOutputUpdateFcns on
	      CombineSignalStateStructs	off
	      SuppressErrorStatus     off
	      ERTFirstTimeCompliant   off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      SupportVariableSizeSignals off
	      EnableShiftOperators    on
	      ParenthesesLevel	      "Nominal"
	      PortableWordSizes	      off
	      ModelStepFunctionPrototypeControlCompliant off
	      CPPClassGenCompliant    on
	      AutosarCompliant	      off
	      GRTInterface	      off
	      UseMalloc		      off
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      ExtModeIntrfLevel	      "Level1"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      RTWCAPIRootIO	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	hdlcoderui.hdlcc {
	  $ObjectID		  13
	  Version		  "1.12.0"
	  Description		  "HDL Coder custom configuration component"
	  Name			  "HDL Coder"
	  Array {
	    Type		    "Cell"
	    Dimension		    1
	    Cell		    " "
	    PropName		    "HDLConfigFile"
	  }
	  HDLCActiveTab		  "0"
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      CurrentDlgPage	      "Solver"
      ConfigPrmDlgPosition     [ 300, 205, 1380, 845 ] 
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    2
  }
  ExplicitPartitioning	  off
  BlockDefaults {
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
    BlockRotation	    0
    BlockMirror		    off
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    UseDisplayTextAsClickCallback off
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  BlockParameterDefaults {
    Block {
      BlockType		      DiscretePulseGenerator
      PulseType		      "Sample based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Period		      "2"
      PulseWidth	      "1"
      PhaseDelay	      "0"
      SampleTime	      "1"
      VectorParams1D	      on
    }
    Block {
      BlockType		      Scope
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      DataFormat	      "Array"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      CollapseMode	      "All dimensions"
      CollapseDim	      "1"
      InputSameDT	      on
      AccumDataTypeStr	      "Inherit: Inherit via internal rule"
      OutMin		      "[]"
      OutMax		      "[]"
      OutDataTypeStr	      "Inherit: Same as first input"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
  }
  System {
    Name		    "TestModel"
    Location		    [6, 56, 1221, 761]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
    TiledPageScale	    1
    ShowPageBoundaries	    off
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    SIDHighWatermark	    "23"
    Block {
      BlockType		      Reference
      Name		      " System Generator"
      SID		      "6"
      Tag		      "genX"
      Ports		      []
      Position		      [147, 32, 197, 82]
      ZOrder		      139
      ShowName		      off
      AttributesFormatString  "System\\nGenerator"
      LibraryVersion	      "1.2"
      UserDataPersistent      on
      UserData		      "DataTag0"
      SourceBlock	      "xbsIndex_r4/ System Generator"
      SourceType	      "Xilinx System Generator Block"
      infoedit		      " System Generator"
      xilinxfamily	      "spartan6"
      part		      "xc6slx25"
      speed		      "-3"
      package		      "ftg256"
      synthesis_tool	      "XST"
      clock_wrapper	      "Clock Enables"
      directory		      "./netlist"
      proj_type		      "Project Navigator"
      Synth_file	      "XST Defaults"
      Impl_file		      "ISE Defaults"
      testbench		      off
      simulink_period	      "1"
      sysclk_period	      "10"
      dcm_input_clock_period  "10"
      incr_netlist	      off
      trim_vbits	      "Everywhere in SubSystem"
      dbl_ovrd		      "According to Block Masks"
      core_generation	      "According to Block Masks"
      run_coregen	      off
      deprecated_control      off
      eval_field	      "0"
      has_advanced_control    "0"
      sggui_pos		      "271,242,464,470"
      block_type	      "sysgen"
      sg_icon_stat	      "50,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]"
      ");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1"
      "55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3"
      "6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15"
      "5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15"
      "5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph"
      "ics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Aumento del Risetime"
      SID		      "7"
      Ports		      [1, 1]
      Position		      [185, 172, 250, 228]
      ZOrder		      143
      LibraryVersion	      "1.320"
      SourceBlock	      "dsparch4/Analog\nFilter Design"
      SourceType	      "Analog Filter Design"
      method		      "Butterworth"
      filttype		      "Lowpass"
      N			      "1"
      Wlo		      "0.01"
      Whi		      "80"
      Rp		      "2"
      Rs		      "40"
      Port {
	PortNumber		1
	Name			"Limitada en BW"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Convert"
      SID		      "22"
      Ports		      [1, 1]
      Position		      [615, 205, 660, 235]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Convert"
      SourceType	      "Xilinx Type Converter Block"
      infoedit		      "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do "
      "not."
      gui_display_data_type   "Fixed-point"
      arith_type	      "Signed  (2's comp)"
      n_bits		      "10"
      bin_pt		      "0"
      float_type	      "Single"
      exp_bits		      "8"
      fraction_bits	      "24"
      quantization	      "Truncate"
      overflow		      "Wrap"
      en		      off
      latency		      "0"
      dbl_ovrd		      off
      pipeline		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "20,21,519,624"
      block_type	      "convert"
      sg_icon_stat	      "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 "
      "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 1"
      "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1"
      " ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.97"
      "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port"
      "_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Filtro"
      SID		      "5"
      Ports		      [1, 2]
      Position		      [530, 154, 590, 241]
      ZOrder		      5
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Black Box"
      SourceType	      "Xilinx Black Box Block"
      infoedit		      " Incorporates black box HDL and simulation model into a System Generator design.<br><br>You mus"
      "t supply a Black Box with certain information about the HDL component you would like to bring into System Genera"
      "tor. This information is provided through a Matlab function.<br><br>When \"Simulation mode\" is set to \"Inactiv"
      "e\", you will typically want to provide a separate simulation model by using a Simulation Multiplexer.<br>When \""
      "Simulation mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design."
      init_code		      "FilterWrapper_config"
      sim_method	      "ISE Simulator"
      verbose		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "20,21,419,454"
      block_type	      "blackbox2"
      sg_icon_stat	      "60,87,1,2,white,blue,0,15bc2c65,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 87 87 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 87 87 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[51.88 "
      "51.88 59.88 51.88 59.88 59.88 59.88 51.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[43.88 43.88 51.88 5"
      "1.88 43.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[35.88 35.88 43.88 43.88 35.88 ],[1 1 1"
      " ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[27.88 27.88 35.88 27.88 35.88 35.88 27.88 ],[0.931 0.946 "
      "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po"
      "rt_label('input',1,'d_i');\ncolor('black');port_label('output',1,'d_o');\ncolor('black');port_label('output',2,'"
      "p_o');\nfprintf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Gateway In"
      SID		      "15"
      Ports		      [1, 1]
      Position		      [405, 190, 470, 210]
      ZOrder		      148
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway In"
      SourceType	      "Xilinx Gateway In Block"
      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to "
      " Xilinx fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top lev"
      "el input ports."
      gui_display_data_type   "Boolean"
      arith_type	      "Boolean"
      n_bits		      "16"
      bin_pt		      "14"
      preci_type	      "Single"
      exp_width		      "8"
      frac_width	      "24"
      quantization	      "Round  (unbiased: +/- Inf)"
      overflow		      "Saturate"
      period		      "1"
      dbl_ovrd		      off
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsADC		      off
      ADCChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      inherit_from_input      off
      hdl_port		      "on"
      has_advanced_control    "0"
      sggui_pos		      "20,26,404,607"
      block_type	      "gatewayin"
      sg_icon_stat	      "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfp"
      "rintf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Gaussian Noise\nGenerator"
      SID		      "8"
      Ports		      [0, 1]
      Position		      [175, 273, 255, 317]
      ZOrder		      142
      LibraryVersion	      "1.74"
      SourceBlock	      "commnoisgen2/Gaussian Noise\nGenerator"
      SourceType	      "Gaussian Noise Generator"
      m			      "0"
      d			      "0.1"
      s			      "123"
      Ts		      "0.1"
      frameBased	      off
      sampPerFrame	      "1"
      orient		      off
      outDataType	      "double"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      SID		      "19"
      Ports		      [4]
      Position		      [825, 65, 910, 240]
      ZOrder		      151
      Floating		      off
      Location		      [75, 57, 1355, 760]
      Open		      off
      NumInputPorts	      "4"
      ZoomMode		      "xonly"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
	axes3			"%<SignalLabel>"
	axes4			"%<SignalLabel>"
      }
      List {
	ListType		ScopeGraphics
	FigureColor		"[0.5 0.5 0.5]"
	AxesColor		"[0 0 0]"
	AxesTickColor		"[1 1 1]"
	LineColors		"[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
	LineStyles		"-|-|-|-|-|-"
	LineWidths		"[0.5 0.5 0.5 0.5 0.5 0.5]"
	MarkerStyles		"none|none|none|none|none|none"
      }
      ShowLegends	      off
      YMin		      "-3~-0.1~-0.1~-50"
      YMax		      "4~1.1~1.1~50"
      LimitDataPoints	      off
    }
    Block {
      BlockType		      Scope
      Name		      "Scope1"
      SID		      "23"
      Ports		      [3]
      Position		      [440, 363, 515, 457]
      ZOrder		      151
      Floating		      off
      Location		      [75, 57, 1355, 760]
      Open		      off
      NumInputPorts	      "3"
      ZoomMode		      "xonly"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
	axes3			"%<SignalLabel>"
      }
      List {
	ListType		ScopeGraphics
	FigureColor		"[0.5 0.5 0.5]"
	AxesColor		"[0 0 0]"
	AxesTickColor		"[1 1 1]"
	LineColors		"[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
	LineStyles		"-|-|-|-|-|-"
	LineWidths		"[0.5 0.5 0.5 0.5 0.5 0.5]"
	MarkerStyles		"none|none|none|none|none|none"
      }
      ShowLegends	      off
      YMin		      "-3~-0.1~-0.1"
      YMax		      "4~1.1~1.1"
      SaveName		      "ScopeData1"
      LimitDataPoints	      off
    }
    Block {
      BlockType		      DiscretePulseGenerator
      Name		      "Senal Original\n"
      SID		      "10"
      Ports		      [0, 1]
      Position		      [80, 184, 110, 216]
      ZOrder		      140
      NamePlacement	      "alternate"
      PulseType		      "Time based"
      Period		      "500"
      PulseWidth	      "50"
      Port {
	PortNumber		1
	Name			"Original"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Senial Interna"
      SID		      "20"
      Ports		      [1, 1]
      Position		      [690, 210, 750, 230]
      ZOrder		      147
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway Out"
      SourceType	      "Xilinx Gateway Out Block"
      infoedit		      "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
      "pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top"
      " level output ports or are discarded, depending on how they are configured."
      inherit_from_input      off
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsDAC		      off
      DACChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "20,26,403,629"
      block_type	      "gatewayout"
      sg_icon_stat	      "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
      "printf('','COMMENT: end icon text');"
      Port {
	PortNumber		1
	Name			"Interna"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Senial Regenerada\n"
      SID		      "14"
      Ports		      [1, 1]
      Position		      [690, 165, 750, 185]
      ZOrder		      147
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway Out"
      SourceType	      "Xilinx Gateway Out Block"
      infoedit		      "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
      "pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top"
      " level output ports or are discarded, depending on how they are configured."
      inherit_from_input      off
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsDAC		      off
      DACChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "20,26,388,578"
      block_type	      "gatewayout"
      sg_icon_stat	      "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
      "printf('','COMMENT: end icon text');"
      Port {
	PortNumber		1
	Name			"Regenerada"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Senial Ruidosa"
      SID		      "21"
      Ports		      [1, 1]
      Position		      [690, 120, 750, 140]
      ZOrder		      147
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway Out"
      SourceType	      "Xilinx Gateway Out Block"
      infoedit		      "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
      "pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top"
      " level output ports or are discarded, depending on how they are configured."
      inherit_from_input      off
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsDAC		      off
      DACChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "20,26,403,629"
      block_type	      "gatewayout"
      sg_icon_stat	      "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
      "printf('','COMMENT: end icon text');"
      Port {
	PortNumber		1
	Name			"Ruido Digital"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
      }
    }
    Block {
      BlockType		      Sum
      Name		      "Sum"
      SID		      "13"
      Ports		      [2, 1]
      Position		      [295, 190, 315, 210]
      ZOrder		      141
      ShowName		      off
      IconShape		      "round"
      Inputs		      "|++"
      InputSameDT	      off
      OutDataTypeStr	      "Inherit: Inherit via internal rule"
      SaturateOnIntegerOverflow	off
      Port {
	PortNumber		1
	Name			"Senal  con ruido"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
      }
    }
    Line {
      SrcBlock		      "Gaussian Noise\nGenerator"
      SrcPort		      1
      Points		      [45, 0]
      DstBlock		      "Sum"
      DstPort		      2
    }
    Line {
      Name		      "Original"
      Labels		      [0, 0]
      SrcBlock		      "Senal Original\n"
      SrcPort		      1
      Points		      [30, 0]
      Branch {
	Labels			[-1, 0]
	DstBlock		"Aumento del Risetime"
	DstPort			1
      }
      Branch {
	Points			[0, 240]
	DstBlock		"Scope1"
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