68 lines
1.1 KiB
VHDL
68 lines
1.1 KiB
VHDL
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
|
|
|
use work.array_functions.all;
|
|
|
|
|
|
|
|
entity FilterWrapper is
|
|
generic (
|
|
CLK_FREQ : integer := 50e6;
|
|
DATA_RATE: integer := 250e3;
|
|
SIMETRIC : boolean := TRUE
|
|
);
|
|
port (
|
|
clk : in std_logic;
|
|
ce: in std_logic;
|
|
|
|
d_i : in std_logic;
|
|
d_o : out std_logic
|
|
);
|
|
end FilterWrapper;
|
|
|
|
architecture Behavioral of FilterWrapper is
|
|
|
|
component Filter is
|
|
|
|
generic (
|
|
CLK_FREQ : integer := 200e6;
|
|
DATA_RATE: integer := 250e3;
|
|
|
|
|
|
SIMETRIC : boolean := TRUE;
|
|
CONSTANTS : array_of_integers := (1,2,3,4,5,6,7,8,9,10)
|
|
|
|
);
|
|
port (
|
|
clk_i : in std_logic;
|
|
enable: in std_logic;
|
|
reset: in std_logic;
|
|
|
|
d_i : in std_logic;
|
|
d_o : out std_logic
|
|
);
|
|
end component;
|
|
|
|
|
|
begin
|
|
|
|
uut: Filter Generic Map(
|
|
CLK_FREQ => CLK_FREQ,
|
|
DATA_RATE => DATA_RATE,
|
|
SIMETRIC => SIMETRIC,
|
|
CONSTANTS => (-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20)
|
|
)
|
|
PORT MAP (
|
|
clk_i => clk,
|
|
enable => ce,
|
|
reset => '0',
|
|
d_i => d_i,
|
|
d_o => d_o
|
|
);
|
|
|
|
|
|
|
|
end Behavioral;
|
|
|