105 lines
3.4 KiB
Matlab
105 lines
3.4 KiB
Matlab
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function FilterWrapper_config(this_block)
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% Revision History:
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%
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% 06-Mar-2017 (15:49 hours):
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% Original code was machine generated by Xilinx's System Generator after parsing
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% /home/epilef/Proyectos/FiltroHDL/FiltroHDL/FilterWrapper.vhd
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%
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%
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this_block.setTopLevelLanguage('VHDL');
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this_block.setEntityName('FilterWrapper');
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% System Generator has to assume that your entity has a combinational feed through;
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% if it doesn't, then comment out the following line:
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this_block.tagAsCombinational;
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this_block.addSimulinkInport('d_i');
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this_block.addSimulinkOutport('d_o');
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d_o_port = this_block.port('d_o');
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d_o_port.setType('UFix_1_0');
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d_o_port.useHDLVector(false);
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% -----------------------------
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if (this_block.inputTypesKnown)
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% do input type checking, dynamic output type and generic setup in this code block.
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if (this_block.port('d_i').width ~= 1);
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this_block.setError('Input data type for port "d_i" must have width=1.');
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end
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this_block.port('d_i').useHDLVector(false);
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end % if(inputTypesKnown)
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% -----------------------------
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% -----------------------------
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if (this_block.inputRatesKnown)
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setup_as_single_rate(this_block,'clk','ce')
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end % if(inputRatesKnown)
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% -----------------------------
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% (!) Set the inout port rate to be the same as the first input
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% rate. Change the following code if this is untrue.
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uniqueInputRates = unique(this_block.getInputRates);
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% (!) Custimize the following generic settings as appropriate. If any settings depend
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% on input types, make the settings in the "inputTypesKnown" code block.
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% The addGeneric function takes 3 parameters, generic name, type and constant value.
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% Supported types are boolean, real, integer and string.
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this_block.addGeneric('CLK_FREQ','integer','1000');
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this_block.addGeneric('DATA_RATE','integer','1');
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this_block.addGeneric('SIMETRIC','boolean','TRUE');
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% Add addtional source files as needed.
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% |-------------
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% | Add files in the order in which they should be compiled.
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% | If two files "a.vhd" and "b.vhd" contain the entities
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% | entity_a and entity_b, and entity_a contains a
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% | component of type entity_b, the correct sequence of
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% | addFile() calls would be:
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% | this_block.addFile('b.vhd');
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% | this_block.addFile('a.vhd');
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% |-------------
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% this_block.addFile('');
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% this_block.addFile('');
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this_block.addFile('../FiltroHDL/array_functions.vhd');
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this_block.addFile('../FiltroHDL/Filter.vhd');
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this_block.addFile('../FiltroHDL/FilterWrapper.vhd');
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return;
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% ------------------------------------------------------------
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function setup_as_single_rate(block,clkname,cename)
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inputRates = block.inputRates;
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uniqueInputRates = unique(inputRates);
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if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf)
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block.addError('The inputs to this block cannot all be constant.');
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return;
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end
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if (uniqueInputRates(end) == Inf)
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hasConstantInput = true;
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uniqueInputRates = uniqueInputRates(1:end-1);
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end
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if (length(uniqueInputRates) ~= 1)
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block.addError('The inputs to this block must run at a single rate.');
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return;
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end
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theInputRate = uniqueInputRates(1);
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for i = 1:block.numSimulinkOutports
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block.outport(i).setRate(theInputRate);
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end
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block.addClkCEPair(clkname,cename,theInputRate);
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return;
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% ------------------------------------------------------------
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