Files
HDLfilter/FiltroTestM/TestModel.mdl
2017-03-07 01:18:29 -03:00

1349 lines
55 KiB
Plaintext

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Created "Mon Mar 06 15:39:53 2017"
Creator "epilef"
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N "1"
Wlo "0.01"
Whi "80"
Rp "2"
Rs "40"
}
Block {
BlockType Reference
Name "Filtro"
SID "5"
Ports [1, 1]
Position [700, 167, 755, 223]
ZOrder 5
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Black Box"
SourceType "Xilinx Black Box Block"
infoedit " Incorporates black box HDL and simulation model into a System Generator design.<br><br>You mus"
"t supply a Black Box with certain information about the HDL component you would like to bring into System Genera"
"tor. This information is provided through a Matlab function.<br><br>When \"Simulation mode\" is set to \"Inactiv"
"e\", you will typically want to provide a separate simulation model by using a Simulation Multiplexer.<br>When \""
"Simulation mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design."
init_code "FilterWrapper_config"
sim_method "ISE Simulator"
verbose off
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "blackbox2"
sg_icon_stat "55,56,1,1,white,blue,0,5474a0b4,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0."
"82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],["
"35.77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 2"
"8.77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28"
".77 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21."
"77 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te"
"xt');\ncolor('black');port_label('input',1,'d_i');\ncolor('black');port_label('output',1,'d_o');\nfprintf('','CO"
"MMENT: end icon text');"
}
Block {
BlockType Reference
Name "Gateway In"
SID "15"
Ports [1, 1]
Position [575, 185, 640, 205]
ZOrder 148
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to "
" Xilinx fixed-point or floating-point data type.<br><br>Hardware notes: In hardware these blocks become top lev"
"el input ports."
gui_display_data_type "Boolean"
arith_type "Boolean"
n_bits "16"
bin_pt "14"
preci_type "Single"
exp_width "8"
frac_width "24"
quantization "Round (unbiased: +/- Inf)"
overflow "Saturate"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
UseAsADC off
ADCChannel "'1'"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
inherit_from_input off
hdl_port "on"
has_advanced_control "0"
sggui_pos "20,26,404,607"
block_type "gatewayin"
sg_icon_stat "65,20,1,1,white,yellow,1,e514e594,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0."
"93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12."
"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 1"
"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
"[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
"port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('red');port_label('output',1,' (!) ');"
"\nfprintf('','COMMENT: end icon text');"
}
Block {
BlockType Reference
Name "Gaussian Noise\nGenerator"
SID "8"
Ports [0, 1]
Position [345, 268, 425, 312]
ZOrder 142
LibraryVersion "1.75"
SourceBlock "commnoisgen2/Gaussian Noise\nGenerator"
SourceType "Gaussian Noise Generator"
ContentPreviewEnabled off
m "0"
d "1.5"
s "123"
Ts "0.1"
frameBased off
sampPerFrame "1"
orient off
outDataType "double"
}
Block {
BlockType Scope
Name "Scope"
SID "19"
Ports [3]
Position [990, 73, 1070, 217]
ZOrder 151
Floating off
Location [122, 140, 1402, 968]
Open on
NumInputPorts "3"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
}
List {
ListType ScopeGraphics
FigureColor "[0.5 0.5 0.5]"
AxesColor "[0 0 0]"
AxesTickColor "[1 1 1]"
LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
LineStyles "-|-|-|-|-|-"
LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]"
MarkerStyles "none|none|none|none|none|none"
}
YMin "-3~-0.1~-0.1"
YMax "4~1.1~1.1"
LimitDataPoints off
}
Block {
BlockType DiscretePulseGenerator
Name "Senal Original\n"
SID "10"
Ports [0, 1]
Position [250, 179, 280, 211]
ZOrder 140
NamePlacement "alternate"
PulseType "Time based"
Period "1000"
PulseWidth "50"
Port {
PortNumber 1
Name "Original"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "Senial Regenerada\n"
SID "14"
Ports [1, 1]
Position [790, 185, 850, 205]
ZOrder 147
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
"pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes: In hardware these blocks become top"
" level output ports or are discarded, depending on how they are configured."
inherit_from_input off
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
UseAsDAC off
DACChannel "'1'"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
has_advanced_control "0"
sggui_pos "20,26,388,578"
block_type "gatewayout"
sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
"93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
"[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
"port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
"printf('','COMMENT: end icon text');"
}
Block {
BlockType Sum
Name "Sum"
SID "13"
Ports [2, 1]
Position [465, 185, 485, 205]
ZOrder 141
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeStr "Inherit: Inherit via internal rule"
SaturateOnIntegerOverflow off
Port {
PortNumber 1
Name "Senal con ruido"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Line {
ZOrder 4
SrcBlock "Gaussian Noise\nGenerator"
SrcPort 1
Points [45, 0]
DstBlock "Sum"
DstPort 2
}
Line {
Name "Original"
ZOrder 9
Labels [0, 0]
SrcBlock "Senal Original\n"
SrcPort 1
Points [30, 0]
Branch {
ZOrder 57
Points [0, -50]
DstBlock "Scope"
DstPort 2
}
Branch {
ZOrder 56
Labels [-1, 0]
DstBlock "Aumento del Risetime"
DstPort 1
}
}
Line {
ZOrder 12
SrcBlock "Aumento del Risetime"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
ZOrder 17
SrcBlock "Filtro"
SrcPort 1
DstBlock "Senial Regenerada\n"
DstPort 1
}
Line {
ZOrder 18
SrcBlock "Gateway In"
SrcPort 1
Points [23, 0]
Branch {
ZOrder 59
Points [0, -100]
DstBlock "Scope"
DstPort 1
}
Branch {
ZOrder 58
DstBlock "Filtro"
DstPort 1
}
}
Line {
ZOrder 35
SrcBlock "Senial Regenerada\n"
SrcPort 1
DstBlock "Scope"
DstPort 3
}
Line {
Name "Senal con ruido"
ZOrder 40
Labels [0, 0]
SrcBlock "Sum"
SrcPort 1
DstBlock "Gateway In"
DstPort 1
}
}
}
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}