124 lines
2.8 KiB
VHDL
124 lines
2.8 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 14:47:13 03/03/2017
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-- Design Name:
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-- Module Name: /home/epilef/Proyectos/FiltroHDL/FiltroHDL/Filter_tb.vhd
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-- Project Name: FiltroHDL
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: Filter
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use work.array_functions.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY Filter_tb IS
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END Filter_tb;
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ARCHITECTURE behavior OF Filter_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Filter
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generic (
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CLK_FREQ : integer := 200e6;
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DATA_RATE: integer := 250e3;
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SIMETRIC : boolean := true;
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CONSTANTS : array_of_integers := (-10,-10,-10,-10,10,10,10,10)
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);
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PORT(
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clk_i : IN std_logic;
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enable : IN std_logic;
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reset : IN std_logic;
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d_i : IN std_logic;
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d_o : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal clk_i : std_logic := '0';
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signal enable : std_logic := '1';
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signal reset : std_logic := '0';
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signal d_i : std_logic := '0';
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--Outputs
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signal d_o : std_logic;
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-- Clock period definitions
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constant clk_i_period : time := 5 ns;
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constant data_period : time := 4 us;
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constant data: std_logic_vector := x"EB901234ABCD5678EF09";
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Filter Generic Map(
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CLK_FREQ => 200e6,
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DATA_RATE => 250e3,
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SIMETRIC => true,
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CONSTANTS => ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
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)
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PORT MAP (
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clk_i => clk_i,
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enable => enable,
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reset => reset,
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d_i => d_i,
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d_o => d_o
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);
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-- Clock process definitions
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clk_i_process :process
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begin
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clk_i <= '0';
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wait for clk_i_period/2;
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clk_i <= '1';
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wait for clk_i_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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for i in 0 to data'length -1 loop
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d_i <= data(i);
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wait for data_period;
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end loop;
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-- insert stimulus here
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wait;
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end process;
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END;
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