fdiniello/HDLfilter
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Se cambió a variables de 12bits
This commit is contained in:
epilef
2017-03-10 09:28:30 -03:00
parent 851f6d40d8
commit 8830cf7589
2 changed files with 6 additions and 4 deletions
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6
FiltroHDL/Filter.vhd
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@@ -44,7 +44,9 @@ architecture Behavioral of Filter is
--~ Acumulador:
signal accum: integer range -MAX_RANGE to MAX_RANGE := 0;
constant INIT_VAL: integer range -MAX_RANGE to MAX_RANGE := 0;
signal accum: integer range -MAX_RANGE to MAX_RANGE := INIT_VAL;
signal i : integer range 0 to N-1 := 0;
signal i_rst : std_logic := '0';
@@ -121,7 +123,7 @@ begin
if ( enable = '1' ) then
if ( i_rst = '1' ) then
i <= 0;
accum <= 0;
accum <= INIT_VAL;
else
if ( i < N-1 ) then

4
FiltroHDL/filter_pkg.vhd
View File

@@ -3,7 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package filter_pkg is
constant MAX_RANGE : integer := 511;
constant MAX_RANGE : integer := 2047;
type array_of_integers is array(integer range <>) of integer range -MAX_RANGE to MAX_RANGE;
@@ -21,7 +21,7 @@ package filter_pkg is
SIMETRIC : boolean := TRUE;
CONSTANTS : array_of_integers := (-4,-3,-2,-1,0,1,2,3,4,5)
CONSTANTS : array_of_integers := (1,2,3,4,5,6,7,8,9,10)
);
port (