fdiniello/HDLfilter
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Cambio de Rango

Browse Source 
Se cambió a variables de 12bits
This commit is contained in:
epilef
2017-03-10 09:28:30 -03:00
parent 851f6d40d8
commit 8830cf7589
2 changed files with 6 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
FiltroHDL/Filter.vhd
View File

@@ -44,7 +44,9 @@ architecture Behavioral of Filter is
--~ Acumulador:
signal accum: integer range -MAX_RANGE to MAX_RANGE := 0;
constant INIT_VAL: integer range -MAX_RANGE to MAX_RANGE := 0;
signal accum: integer range -MAX_RANGE to MAX_RANGE := INIT_VAL;
signal i : integer range 0 to N-1 := 0;
signal i_rst : std_logic := '0';
@@ -121,7 +123,7 @@ begin
if ( enable = '1' ) then
if ( i_rst = '1' ) then
i <= 0;
accum <= 0;
accum <= INIT_VAL;
else
if ( i < N-1 ) then