79 lines
1.7 KiB
VHDL
79 lines
1.7 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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package filter_pkg is
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constant MAX_RANGE : integer := 2047;
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type array_of_integers is array(integer range <>) of integer range -MAX_RANGE to MAX_RANGE;
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function array_sum ( K : in array_of_integers )
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return integer;
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function reorder_array ( K : in array_of_integers ; simetric : in boolean )
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return array_of_integers;
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component Filter is
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generic (
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CLK_FREQ : integer := 200e6;
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DATA_RATE: integer := 250e3;
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SIMETRIC : boolean := TRUE;
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CONSTANTS : array_of_integers := (1,2,3,4,5,6,7,8,9,10)
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);
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port (
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clk_i : in std_logic;
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enable: in std_logic;
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reset: in std_logic;
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d_i : in std_logic;
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d_o : out std_logic;
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p_o : out std_logic_vector(9 downto 0)
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);
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end component;
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end package;
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package body filter_pkg is
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function array_sum ( K : in array_of_integers ) return integer is
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variable sum : integer := 0;
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begin
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for i in 0 to K'length-1 loop
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sum := sum + K(K'left + i);
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end loop;
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return sum;
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end array_sum;
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function reorder_array ( K : in array_of_integers ; simetric : in boolean )
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return array_of_integers is
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constant M : integer := 1 + 2*((K'length)-1);
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constant N : integer := K'length;
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variable arr_s : array_of_integers( 0 to M-1 );
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variable arr_a : array_of_integers( 0 to N-1 );
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begin
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if ( simetric ) then
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for i in 0 to N-1 loop
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arr_s( i ) := K( K'left + i );
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end loop;
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for i in 1 to N-1 loop
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arr_s( n + i - 1 ) := K( K'right - i );
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end loop;
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return arr_s;
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else
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for i in 0 to N-1 loop
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arr_a( i ) := K( K'left + i );
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end loop;
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return arr_a;
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end if;
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end reorder_array;
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end filter_pkg;
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