1447 lines
60 KiB
Plaintext
1447 lines
60 KiB
Plaintext
Model {
|
|
Name "TestModel"
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|
Version 7.9
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|
MdlSubVersion 0
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GraphicalInterface {
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NumRootInports 0
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NumRootOutports 0
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ParameterArgumentNames ""
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ComputedModelVersion "1.62"
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NumModelReferences 0
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NumTestPointedSignals 0
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}
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SavedCharacterEncoding "US-ASCII"
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SaveDefaultBlockParams on
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|
ScopeRefreshTime 0.035000
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OverrideScopeRefreshTime on
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DisableAllScopes on
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DataTypeOverride "UseLocalSettings"
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DataTypeOverrideAppliesTo "AllNumericTypes"
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MinMaxOverflowLogging "UseLocalSettings"
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MinMaxOverflowArchiveMode "Overwrite"
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|
FPTRunName "Run 1"
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MaxMDLFileLineLength 120
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Created "Mon Mar 06 15:39:53 2017"
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Creator "epilef"
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UpdateHistory "UpdateHistoryNever"
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ModifiedByFormat "%<Auto>"
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LastModifiedBy "epilef"
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ModifiedDateFormat "%<Auto>"
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LastModifiedDate "Wed Mar 08 13:52:04 2017"
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RTWModifiedTimeStamp 410871668
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ModelVersionFormat "1.%<AutoIncrement:62>"
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ConfigurationManager "none"
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SampleTimeColors off
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SampleTimeAnnotations off
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LibraryLinkDisplay "disabled"
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WideLines off
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ShowLineDimensions off
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ShowPortDataTypes off
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ShowDesignRanges off
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ShowLoopsOnError on
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IgnoreBidirectionalLines off
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ShowStorageClass off
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ShowTestPointIcons on
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ShowSignalResolutionIcons on
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ShowViewerIcons on
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SortedOrder off
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ExecutionContextIcon off
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ShowLinearizationAnnotations on
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BlockNameDataTip off
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BlockParametersDataTip off
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BlockDescriptionStringDataTip off
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ToolBar on
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StatusBar on
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BrowserShowLibraryLinks off
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BrowserLookUnderMasks off
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SimulationMode "normal"
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LinearizationMsg "none"
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Profile off
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ParamWorkspaceSource "MATLABWorkspace"
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AccelSystemTargetFile "accel.tlc"
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AccelTemplateMakefile "accel_default_tmf"
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AccelMakeCommand "make_rtw"
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TryForcingSFcnDF off
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Object {
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$PropName "DataLoggingOverride"
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$ObjectID 1
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$ClassName "Simulink.SimulationData.ModelLoggingInfo"
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model_ "TestModel"
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signals_ []
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overrideMode_ [0.0]
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Array {
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Type "Cell"
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Dimension 1
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Cell "TestModel"
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PropName "logAsSpecifiedByModels_"
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}
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Array {
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Type "Cell"
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Dimension 1
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Cell []
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PropName "logAsSpecifiedByModelsSSIDs_"
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}
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}
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RecordCoverage off
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CovPath "/"
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CovSaveName "covdata"
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CovMetricSettings "dw"
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CovNameIncrementing off
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CovHtmlReporting on
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CovForceBlockReductionOff on
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covSaveCumulativeToWorkspaceVar on
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CovSaveSingleToWorkspaceVar on
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CovCumulativeVarName "covCumulativeData"
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CovCumulativeReport off
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CovReportOnPause on
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CovModelRefEnable "Off"
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CovExternalEMLEnable off
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ExtModeBatchMode off
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ExtModeEnableFloating on
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ExtModeTrigType "manual"
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ExtModeTrigMode "normal"
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ExtModeTrigPort "1"
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ExtModeTrigElement "any"
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ExtModeTrigDuration 1000
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ExtModeTrigDurationFloating "auto"
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ExtModeTrigHoldOff 0
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ExtModeTrigDelay 0
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ExtModeTrigDirection "rising"
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ExtModeTrigLevel 0
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ExtModeArchiveMode "off"
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ExtModeAutoIncOneShot off
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ExtModeIncDirWhenArm off
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ExtModeAddSuffixToVar off
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ExtModeWriteAllDataToWs off
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ExtModeArmWhenConnect on
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ExtModeSkipDownloadWhenConnect off
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ExtModeLogAll on
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ExtModeAutoUpdateStatusClock on
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BufferReuse on
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ShowModelReferenceBlockVersion off
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ShowModelReferenceBlockIO off
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Array {
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Type "Handle"
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Dimension 1
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Simulink.ConfigSet {
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$ObjectID 2
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Version "1.12.0"
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Array {
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Type "Handle"
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Dimension 9
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Simulink.SolverCC {
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$ObjectID 3
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Version "1.12.0"
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StartTime "0.0"
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StopTime "5000"
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AbsTol "auto"
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FixedStep "auto"
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InitialStep "auto"
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MaxNumMinSteps "-1"
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MaxOrder 5
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ZcThreshold "auto"
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ConsecutiveZCsStepRelTol "10*128*eps"
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MaxConsecutiveZCs "1000"
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ExtrapolationOrder 4
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NumberNewtonIterations 1
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MaxStep "auto"
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MinStep "auto"
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MaxConsecutiveMinStep "1"
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RelTol "1e-3"
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SolverMode "Auto"
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EnableConcurrentExecution off
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ConcurrentTasks off
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Solver "ode45"
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SolverName "ode45"
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SolverJacobianMethodControl "auto"
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ShapePreserveControl "DisableAll"
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ZeroCrossControl "UseLocalSettings"
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ZeroCrossAlgorithm "Nonadaptive"
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AlgebraicLoopSolver "TrustRegion"
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SolverResetMethod "Fast"
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PositivePriorityOrder off
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AutoInsertRateTranBlk off
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SampleTimeConstraint "Unconstrained"
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InsertRTBMode "Whenever possible"
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}
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Simulink.DataIOCC {
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$ObjectID 4
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Version "1.12.0"
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Decimation "1"
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ExternalInput "[t, u]"
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FinalStateName "xFinal"
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InitialState "xInitial"
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LimitDataPoints on
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MaxDataPoints "1000"
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LoadExternalInput off
|
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LoadInitialState off
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SaveFinalState off
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SaveCompleteFinalSimState off
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SaveFormat "Array"
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SignalLoggingSaveFormat "Dataset"
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SaveOutput on
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SaveState off
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SignalLogging on
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DSMLogging on
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InspectSignalLogs off
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SaveTime on
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ReturnWorkspaceOutputs off
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StateSaveName "xout"
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TimeSaveName "tout"
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OutputSaveName "yout"
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SignalLoggingName "logsout"
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DSMLoggingName "dsmout"
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OutputOption "RefineOutputTimes"
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OutputTimes "[]"
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ReturnWorkspaceOutputsName "out"
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Refine "1"
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|
}
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Simulink.OptimizationCC {
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$ObjectID 5
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Version "1.12.0"
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Array {
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Type "Cell"
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Dimension 8
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Cell "BooleansAsBitfields"
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Cell "PassReuseOutputArgsAs"
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Cell "PassReuseOutputArgsThreshold"
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Cell "ZeroExternalMemoryAtStartup"
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Cell "ZeroInternalMemoryAtStartup"
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Cell "OptimizeModelRefInitCode"
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Cell "NoFixptDivByZeroProtection"
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Cell "UseSpecifiedMinMax"
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PropName "DisabledProps"
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}
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BlockReduction on
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BooleanDataType on
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ConditionallyExecuteInputs on
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InlineParams off
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UseIntDivNetSlope off
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UseFloatMulNetSlope off
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UseSpecifiedMinMax off
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InlineInvariantSignals off
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OptimizeBlockIOStorage on
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BufferReuse on
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EnhancedBackFolding off
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StrengthReduction off
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ExpressionFolding on
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BooleansAsBitfields off
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BitfieldContainerType "uint_T"
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EnableMemcpy on
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MemcpyThreshold 64
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PassReuseOutputArgsAs "Structure reference"
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ExpressionDepthLimit 128
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FoldNonRolledExpr on
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LocalBlockOutputs on
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RollThreshold 5
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SystemCodeInlineAuto off
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StateBitsets off
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DataBitsets off
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UseTempVars off
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ZeroExternalMemoryAtStartup on
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ZeroInternalMemoryAtStartup on
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InitFltsAndDblsToZero off
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NoFixptDivByZeroProtection off
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EfficientFloat2IntCast off
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EfficientMapNaN2IntZero on
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OptimizeModelRefInitCode off
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LifeSpan "inf"
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MaxStackSize "Inherit from target"
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BufferReusableBoundary on
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SimCompilerOptimization "Off"
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AccelVerboseBuild off
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ParallelExecutionInRapidAccelerator on
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}
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Simulink.DebuggingCC {
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$ObjectID 6
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Version "1.12.0"
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RTPrefix "error"
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ConsistencyChecking "none"
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ArrayBoundsChecking "none"
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SignalInfNanChecking "none"
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SignalRangeChecking "none"
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ReadBeforeWriteMsg "UseLocalSettings"
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WriteAfterWriteMsg "UseLocalSettings"
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WriteAfterReadMsg "UseLocalSettings"
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AlgebraicLoopMsg "warning"
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ArtificialAlgebraicLoopMsg "warning"
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SaveWithDisabledLinksMsg "warning"
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SaveWithParameterizedLinksMsg "warning"
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CheckSSInitialOutputMsg on
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UnderspecifiedInitializationDetection "Simplified"
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MergeDetectMultiDrivingBlocksExec "error"
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CheckExecutionContextPreStartOutputMsg off
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CheckExecutionContextRuntimeOutputMsg off
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SignalResolutionControl "UseLocalSettings"
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BlockPriorityViolationMsg "warning"
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MinStepSizeMsg "warning"
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TimeAdjustmentMsg "none"
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MaxConsecutiveZCsMsg "error"
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MaskedZcDiagnostic "warning"
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IgnoredZcDiagnostic "warning"
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SolverPrmCheckMsg "none"
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InheritedTsInSrcMsg "warning"
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DiscreteInheritContinuousMsg "warning"
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MultiTaskDSMMsg "error"
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MultiTaskCondExecSysMsg "error"
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MultiTaskRateTransMsg "error"
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SingleTaskRateTransMsg "none"
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TasksWithSamePriorityMsg "warning"
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SigSpecEnsureSampleTimeMsg "warning"
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CheckMatrixSingularityMsg "none"
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IntegerOverflowMsg "warning"
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Int32ToFloatConvMsg "warning"
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ParameterDowncastMsg "error"
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ParameterOverflowMsg "error"
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ParameterUnderflowMsg "none"
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ParameterPrecisionLossMsg "warning"
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ParameterTunabilityLossMsg "warning"
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FixptConstUnderflowMsg "none"
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FixptConstOverflowMsg "none"
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FixptConstPrecisionLossMsg "none"
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UnderSpecifiedDataTypeMsg "none"
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UnnecessaryDatatypeConvMsg "none"
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VectorMatrixConversionMsg "none"
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InvalidFcnCallConnMsg "error"
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FcnCallInpInsideContextMsg "Enable All"
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SignalLabelMismatchMsg "none"
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UnconnectedInputMsg "warning"
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UnconnectedOutputMsg "warning"
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UnconnectedLineMsg "warning"
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SFcnCompatibilityMsg "none"
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FrameProcessingCompatibilityMsg "error"
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UniqueDataStoreMsg "none"
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BusObjectLabelMismatch "warning"
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RootOutportRequireBusObject "warning"
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AssertControl "UseLocalSettings"
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EnableOverflowDetection off
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ModelReferenceIOMsg "none"
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ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error"
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ModelReferenceVersionMismatchMessage "none"
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ModelReferenceIOMismatchMessage "none"
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ModelReferenceCSMismatchMessage "none"
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UnknownTsInhSupMsg "warning"
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ModelReferenceDataLoggingMessage "warning"
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ModelReferenceSymbolNameMessage "warning"
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ModelReferenceExtraNoncontSigs "error"
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StateNameClashWarn "none"
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SimStateInterfaceChecksumMismatchMsg "warning"
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SimStateOlderReleaseMsg "error"
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InitInArrayFormatMsg "warning"
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StrictBusMsg "ErrorLevel1"
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BusNameAdapt "WarnAndRepair"
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NonBusSignalsTreatedAsBus "none"
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LoggingUnavailableSignals "error"
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BlockIODiagnostic "none"
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SFUnusedDataAndEventsDiag "warning"
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SFUnexpectedBacktrackingDiag "warning"
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SFInvalidInputDataAccessInChartInitDiag "warning"
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SFNoUnconditionalDefaultTransitionDiag "warning"
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SFTransitionOutsideNaturalParentDiag "warning"
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SFUnconditionalTransitionShadowingDiag "warning"
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}
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Simulink.HardwareCC {
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$ObjectID 7
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Version "1.12.0"
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ProdBitPerChar 8
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ProdBitPerShort 16
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ProdBitPerInt 32
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ProdBitPerLong 32
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ProdBitPerFloat 32
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ProdBitPerDouble 64
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ProdBitPerPointer 32
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ProdLargestAtomicInteger "Char"
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ProdLargestAtomicFloat "None"
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ProdIntDivRoundTo "Undefined"
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ProdEndianess "Unspecified"
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ProdWordSize 32
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ProdShiftRightIntArith on
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ProdHWDeviceType "32-bit Generic"
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TargetBitPerChar 8
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TargetBitPerShort 16
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TargetBitPerInt 32
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TargetBitPerLong 32
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TargetBitPerFloat 32
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TargetBitPerDouble 64
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TargetBitPerPointer 32
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TargetLargestAtomicInteger "Char"
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TargetLargestAtomicFloat "None"
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TargetShiftRightIntArith on
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TargetIntDivRoundTo "Undefined"
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TargetEndianess "Unspecified"
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TargetWordSize 32
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TargetTypeEmulationWarnSuppressLevel 0
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TargetPreprocMaxBitsSint 32
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TargetPreprocMaxBitsUint 32
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TargetHWDeviceType "Specified"
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TargetUnknown off
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ProdEqTarget on
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}
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Simulink.ModelReferenceCC {
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$ObjectID 8
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Version "1.12.0"
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UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
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CheckModelReferenceTargetMessage "error"
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EnableParallelModelReferenceBuilds off
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ParallelModelReferenceErrorOnInvalidPool on
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ParallelModelReferenceMATLABWorkerInit "None"
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ModelReferenceNumInstancesAllowed "Multi"
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PropagateVarSize "Infer from blocks in model"
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ModelReferencePassRootInputsByReference on
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ModelReferenceMinAlgLoopOccurrences off
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PropagateSignalLabelsOutOfModel off
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SupportModelReferenceSimTargetCustomCode off
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}
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Simulink.SFSimCC {
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$ObjectID 9
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Version "1.12.0"
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SFSimEnableDebug on
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SFSimOverflowDetection on
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SFSimEcho on
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SimBlas on
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SimCtrlC on
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SimExtrinsic on
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SimIntegrity on
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SimUseLocalCustomCode off
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SimParseCustomCode on
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SimBuildMode "sf_incremental_build"
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}
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Simulink.RTWCC {
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$BackupClass "Simulink.RTWCC"
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$ObjectID 10
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Version "1.12.0"
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Array {
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Type "Cell"
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Dimension 16
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Cell "IncludeHyperlinkInReport"
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Cell "GenerateTraceInfo"
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Cell "GenerateTraceReport"
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Cell "GenerateTraceReportSl"
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Cell "GenerateTraceReportSf"
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Cell "GenerateTraceReportEml"
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Cell "PortableWordSizes"
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Cell "GenerateWebview"
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Cell "GenerateCodeMetricsReport"
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Cell "GenerateCodeReplacementReport"
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Cell "GenerateMissedCodeReplacementReport"
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Cell "GenerateErtSFunction"
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Cell "CreateSILPILBlock"
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Cell "CodeExecutionProfiling"
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Cell "CodeProfilingSaveOptions"
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Cell "CodeProfilingInstrumentation"
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PropName "DisabledProps"
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}
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SystemTargetFile "grt.tlc"
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GenCodeOnly off
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MakeCommand "make_rtw"
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GenerateMakefile on
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TemplateMakefile "grt_default_tmf"
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GenerateReport off
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SaveLog off
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RTWVerbose on
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RetainRTWFile off
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ProfileTLC off
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TLCDebug off
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TLCCoverage off
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TLCAssert off
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ProcessScriptMode "Default"
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ConfigurationMode "Optimized"
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ConfigAtBuild off
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RTWUseLocalCustomCode off
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RTWUseSimCustomCode off
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IncludeHyperlinkInReport off
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LaunchReport off
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TargetLang "C"
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IncludeBusHierarchyInRTWFileBlockHierarchyMap off
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IncludeERTFirstTime off
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GenerateTraceInfo off
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GenerateTraceReport off
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GenerateTraceReportSl off
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GenerateTraceReportSf off
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GenerateTraceReportEml off
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GenerateCodeInfo off
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GenerateWebview off
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GenerateCodeMetricsReport off
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GenerateCodeReplacementReport off
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RTWCompilerOptimization "Off"
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CheckMdlBeforeBuild "Off"
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CustomRebuildMode "OnUpdate"
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Array {
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Type "Handle"
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Dimension 2
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Simulink.CodeAppCC {
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$ObjectID 11
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Version "1.12.0"
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Array {
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Type "Cell"
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Dimension 24
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Cell "IgnoreCustomStorageClasses"
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Cell "ParameterTuningSideEffectCode"
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Cell "IgnoreTestpoints"
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Cell "InsertBlockDesc"
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Cell "InsertPolySpaceComments"
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Cell "SFDataObjDesc"
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Cell "MATLABFcnDesc"
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Cell "SimulinkDataObjDesc"
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Cell "DefineNamingRule"
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Cell "SignalNamingRule"
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Cell "ParamNamingRule"
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Cell "InternalIdentifier"
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Cell "InlinedPrmAccess"
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Cell "CustomSymbolStr"
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Cell "CustomSymbolStrGlobalVar"
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Cell "CustomSymbolStrType"
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Cell "CustomSymbolStrField"
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Cell "CustomSymbolStrFcn"
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Cell "CustomSymbolStrFcnArg"
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Cell "CustomSymbolStrBlkIO"
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Cell "CustomSymbolStrTmpVar"
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Cell "CustomSymbolStrMacro"
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Cell "CustomSymbolStrUtil"
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Cell "ReqsInCode"
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PropName "DisabledProps"
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}
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ForceParamTrailComments off
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GenerateComments on
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IgnoreCustomStorageClasses on
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IgnoreTestpoints off
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IncHierarchyInIds off
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MaxIdLength 31
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PreserveName off
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PreserveNameWithParent off
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ShowEliminatedStatement off
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IncAutoGenComments off
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SimulinkDataObjDesc off
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SFDataObjDesc off
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MATLABFcnDesc off
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IncDataTypeInIds off
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MangleLength 1
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CustomSymbolStrGlobalVar "$R$N$M"
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CustomSymbolStrType "$N$R$M_T"
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CustomSymbolStrField "$N$M"
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CustomSymbolStrFcn "$R$N$M$F"
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CustomSymbolStrFcnArg "rt$I$N$M"
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CustomSymbolStrBlkIO "rtb_$N$M"
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CustomSymbolStrTmpVar "$N$M"
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CustomSymbolStrMacro "$R$N$M"
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DefineNamingRule "None"
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ParamNamingRule "None"
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SignalNamingRule "None"
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InsertBlockDesc off
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InsertPolySpaceComments off
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SimulinkBlockComments on
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MATLABSourceComments off
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EnableCustomComments off
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InlinedPrmAccess "Literals"
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ReqsInCode off
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UseSimReservedNames off
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}
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Simulink.GRTTargetCC {
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$BackupClass "Simulink.TargetCC"
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$ObjectID 12
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Version "1.12.0"
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Array {
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Type "Cell"
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Dimension 13
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Cell "GeneratePreprocessorConditionals"
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Cell "IncludeMdlTerminateFcn"
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Cell "SuppressErrorStatus"
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Cell "ERTCustomFileBanners"
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Cell "GenerateSampleERTMain"
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|
Cell "GenerateTestInterfaces"
|
|
Cell "ModelStepFunctionPrototypeControlCompliant"
|
|
Cell "GenerateAllocFcn"
|
|
Cell "PurelyIntegerCode"
|
|
Cell "SupportComplex"
|
|
Cell "SupportAbsoluteTime"
|
|
Cell "SupportContinuousTime"
|
|
Cell "SupportNonInlinedSFcns"
|
|
PropName "DisabledProps"
|
|
}
|
|
TargetFcnLib "ansi_tfl_table_tmw.mat"
|
|
TargetLibSuffix ""
|
|
TargetPreCompLibLocation ""
|
|
CodeReplacementLibrary "None"
|
|
UtilityFuncGeneration "Auto"
|
|
ERTMultiwordTypeDef "System defined"
|
|
CodeExecutionProfiling off
|
|
ERTMultiwordLength 256
|
|
MultiwordLength 2048
|
|
GenerateFullHeader on
|
|
GenerateSampleERTMain off
|
|
GenerateTestInterfaces off
|
|
IsPILTarget off
|
|
ModelReferenceCompliant on
|
|
ParMdlRefBuildCompliant on
|
|
CompOptLevelCompliant on
|
|
ConcurrentExecutionCompliant on
|
|
IncludeMdlTerminateFcn on
|
|
GeneratePreprocessorConditionals "Disable all"
|
|
CombineOutputUpdateFcns on
|
|
CombineSignalStateStructs off
|
|
SuppressErrorStatus off
|
|
ERTFirstTimeCompliant off
|
|
IncludeFileDelimiter "Auto"
|
|
ERTCustomFileBanners off
|
|
SupportAbsoluteTime on
|
|
LogVarNameModifier "rt_"
|
|
MatFileLogging on
|
|
MultiInstanceERTCode off
|
|
SupportNonFinite on
|
|
SupportComplex on
|
|
PurelyIntegerCode off
|
|
SupportContinuousTime on
|
|
SupportNonInlinedSFcns on
|
|
SupportVariableSizeSignals off
|
|
EnableShiftOperators on
|
|
ParenthesesLevel "Nominal"
|
|
PortableWordSizes off
|
|
ModelStepFunctionPrototypeControlCompliant off
|
|
CPPClassGenCompliant on
|
|
AutosarCompliant off
|
|
GRTInterface off
|
|
UseMalloc off
|
|
ExtMode off
|
|
ExtModeStaticAlloc off
|
|
ExtModeTesting off
|
|
ExtModeStaticAllocSize 1000000
|
|
ExtModeTransport 0
|
|
ExtModeMexFile "ext_comm"
|
|
ExtModeIntrfLevel "Level1"
|
|
RTWCAPISignals off
|
|
RTWCAPIParams off
|
|
RTWCAPIStates off
|
|
RTWCAPIRootIO off
|
|
GenerateASAP2 off
|
|
}
|
|
PropName "Components"
|
|
}
|
|
}
|
|
hdlcoderui.hdlcc {
|
|
$ObjectID 13
|
|
Version "1.12.0"
|
|
Description "HDL Coder custom configuration component"
|
|
Name "HDL Coder"
|
|
Array {
|
|
Type "Cell"
|
|
Dimension 1
|
|
Cell " "
|
|
PropName "HDLConfigFile"
|
|
}
|
|
HDLCActiveTab "0"
|
|
}
|
|
PropName "Components"
|
|
}
|
|
Name "Configuration"
|
|
CurrentDlgPage "Solver"
|
|
ConfigPrmDlgPosition [ 300, 205, 1380, 845 ]
|
|
}
|
|
PropName "ConfigurationSets"
|
|
}
|
|
Simulink.ConfigSet {
|
|
$PropName "ActiveConfigurationSet"
|
|
$ObjectID 2
|
|
}
|
|
ExplicitPartitioning off
|
|
BlockDefaults {
|
|
ForegroundColor "black"
|
|
BackgroundColor "white"
|
|
DropShadow off
|
|
NamePlacement "normal"
|
|
FontName "Helvetica"
|
|
FontSize 10
|
|
FontWeight "normal"
|
|
FontAngle "normal"
|
|
ShowName on
|
|
BlockRotation 0
|
|
BlockMirror off
|
|
}
|
|
AnnotationDefaults {
|
|
HorizontalAlignment "center"
|
|
VerticalAlignment "middle"
|
|
ForegroundColor "black"
|
|
BackgroundColor "white"
|
|
DropShadow off
|
|
FontName "Helvetica"
|
|
FontSize 10
|
|
FontWeight "normal"
|
|
FontAngle "normal"
|
|
UseDisplayTextAsClickCallback off
|
|
}
|
|
LineDefaults {
|
|
FontName "Helvetica"
|
|
FontSize 9
|
|
FontWeight "normal"
|
|
FontAngle "normal"
|
|
}
|
|
BlockParameterDefaults {
|
|
Block {
|
|
BlockType DiscretePulseGenerator
|
|
PulseType "Sample based"
|
|
TimeSource "Use simulation time"
|
|
Amplitude "1"
|
|
Period "2"
|
|
PulseWidth "1"
|
|
PhaseDelay "0"
|
|
SampleTime "1"
|
|
VectorParams1D on
|
|
}
|
|
Block {
|
|
BlockType Scope
|
|
ModelBased off
|
|
TickLabels "OneTimeTick"
|
|
ZoomMode "on"
|
|
Grid "on"
|
|
TimeRange "auto"
|
|
YMin "-5"
|
|
YMax "5"
|
|
SaveToWorkspace off
|
|
SaveName "ScopeData"
|
|
DataFormat "Array"
|
|
LimitDataPoints on
|
|
MaxDataPoints "5000"
|
|
Decimation "1"
|
|
SampleInput off
|
|
SampleTime "-1"
|
|
}
|
|
Block {
|
|
BlockType Sum
|
|
IconShape "rectangular"
|
|
Inputs "++"
|
|
CollapseMode "All dimensions"
|
|
CollapseDim "1"
|
|
InputSameDT on
|
|
AccumDataTypeStr "Inherit: Inherit via internal rule"
|
|
OutMin "[]"
|
|
OutMax "[]"
|
|
OutDataTypeStr "Inherit: Same as first input"
|
|
LockScale off
|
|
RndMeth "Floor"
|
|
SaturateOnIntegerOverflow on
|
|
SampleTime "-1"
|
|
}
|
|
}
|
|
System {
|
|
Name "TestModel"
|
|
Location [6, 56, 1221, 761]
|
|
Open on
|
|
ModelBrowserVisibility off
|
|
ModelBrowserWidth 200
|
|
ScreenColor "white"
|
|
PaperOrientation "landscape"
|
|
PaperPositionMode "auto"
|
|
PaperType "usletter"
|
|
PaperUnits "inches"
|
|
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
|
|
TiledPageScale 1
|
|
ShowPageBoundaries off
|
|
ZoomFactor "100"
|
|
ReportName "simulink-default.rpt"
|
|
SIDHighWatermark "23"
|
|
Block {
|
|
BlockType Reference
|
|
Name " System Generator"
|
|
SID "6"
|
|
Tag "genX"
|
|
Ports []
|
|
Position [147, 32, 197, 82]
|
|
ZOrder 139
|
|
ShowName off
|
|
AttributesFormatString "System\\nGenerator"
|
|
LibraryVersion "1.2"
|
|
UserDataPersistent on
|
|
UserData "DataTag0"
|
|
SourceBlock "xbsIndex_r4/ System Generator"
|
|
SourceType "Xilinx System Generator Block"
|
|
infoedit " System Generator"
|
|
xilinxfamily "spartan6"
|
|
part "xc6slx25"
|
|
speed "-3"
|
|
package "ftg256"
|
|
synthesis_tool "XST"
|
|
clock_wrapper "Clock Enables"
|
|
directory "./netlist"
|
|
proj_type "Project Navigator"
|
|
Synth_file "XST Defaults"
|
|
Impl_file "ISE Defaults"
|
|
testbench off
|
|
simulink_period "1"
|
|
sysclk_period "10"
|
|
dcm_input_clock_period "10"
|
|
incr_netlist off
|
|
trim_vbits "Everywhere in SubSystem"
|
|
dbl_ovrd "According to Block Masks"
|
|
core_generation "According to Block Masks"
|
|
run_coregen off
|
|
deprecated_control off
|
|
eval_field "0"
|
|
has_advanced_control "0"
|
|
sggui_pos "271,242,464,470"
|
|
block_type "sysgen"
|
|
sg_icon_stat "50,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]"
|
|
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]"
|
|
");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1"
|
|
"55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3"
|
|
"6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15"
|
|
"5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15"
|
|
"5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph"
|
|
"ics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');"
|
|
}
|
|
Block {
|
|
BlockType Reference
|
|
Name "Aumento del Risetime"
|
|
SID "7"
|
|
Ports [1, 1]
|
|
Position [185, 172, 250, 228]
|
|
ZOrder 143
|
|
LibraryVersion "1.320"
|
|
SourceBlock "dsparch4/Analog\nFilter Design"
|
|
SourceType "Analog Filter Design"
|
|
method "Butterworth"
|
|
filttype "Lowpass"
|
|
N "1"
|
|
Wlo "0.01"
|
|
Whi "80"
|
|
Rp "2"
|
|
Rs "40"
|
|
Port {
|
|
PortNumber 1
|
|
Name "Limitada en BW"
|
|
RTWStorageClass "Auto"
|
|
DataLoggingNameMode "SignalName"
|
|
}
|
|
}
|
|
Block {
|
|
BlockType Reference
|
|
Name "Convert"
|
|
SID "22"
|
|
Ports [1, 1]
|
|
Position [615, 205, 660, 235]
|
|
LibraryVersion "1.2"
|
|
SourceBlock "xbsIndex_r4/Convert"
|
|
SourceType "Xilinx Type Converter Block"
|
|
infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do "
|
|
"not."
|
|
gui_display_data_type "Fixed-point"
|
|
arith_type "Signed (2's comp)"
|
|
n_bits "10"
|
|
bin_pt "0"
|
|
float_type "Single"
|
|
exp_bits "8"
|
|
fraction_bits "24"
|
|
quantization "Truncate"
|
|
overflow "Wrap"
|
|
en off
|
|
latency "0"
|
|
dbl_ovrd off
|
|
pipeline off
|
|
xl_use_area off
|
|
xl_area "[0,0,0,0,0,0,0]"
|
|
has_advanced_control "0"
|
|
sggui_pos "20,21,519,624"
|
|
block_type "convert"
|
|
sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]"
|
|
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0."
|
|
"82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 "
|
|
"19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 1"
|
|
"9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1"
|
|
" ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.97"
|
|
"3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port"
|
|
"_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');"
|
|
}
|
|
Block {
|
|
BlockType Reference
|
|
Name "Filtro"
|
|
SID "5"
|
|
Ports [1, 2]
|
|
Position [530, 154, 590, 241]
|
|
ZOrder 5
|
|
LibraryVersion "1.2"
|
|
SourceBlock "xbsIndex_r4/Black Box"
|
|
SourceType "Xilinx Black Box Block"
|
|
infoedit " Incorporates black box HDL and simulation model into a System Generator design.<br><br>You mus"
|
|
"t supply a Black Box with certain information about the HDL component you would like to bring into System Genera"
|
|
"tor. This information is provided through a Matlab function.<br><br>When \"Simulation mode\" is set to \"Inactiv"
|
|
"e\", you will typically want to provide a separate simulation model by using a Simulation Multiplexer.<br>When \""
|
|
"Simulation mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design."
|
|
init_code "FilterWrapper_config"
|
|
sim_method "ISE Simulator"
|
|
verbose off
|
|
xl_use_area off
|
|
xl_area "[0,0,0,0,0,0,0]"
|
|
has_advanced_control "0"
|
|
sggui_pos "20,21,419,454"
|
|
block_type "blackbox2"
|
|
sg_icon_stat "60,87,1,2,white,blue,0,15bc2c65,right,,[ ],[ ]"
|
|
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 87 87 0 ],[0.77 0."
|
|
"82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 87 87 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[51.88 "
|
|
"51.88 59.88 51.88 59.88 59.88 59.88 51.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[43.88 43.88 51.88 5"
|
|
"1.88 43.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[35.88 35.88 43.88 43.88 35.88 ],[1 1 1"
|
|
" ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[27.88 27.88 35.88 27.88 35.88 35.88 27.88 ],[0.931 0.946 "
|
|
"0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po"
|
|
"rt_label('input',1,'d_i');\ncolor('black');port_label('output',1,'d_o');\ncolor('black');port_label('output',2,'"
|
|
"p_o');\nfprintf('','COMMENT: end icon text');"
|
|
}
|
|
Block {
|
|
BlockType Reference
|
|
Name "Gateway In"
|
|
SID "15"
|
|
Ports [1, 1]
|
|
Position [405, 190, 470, 210]
|
|
ZOrder 148
|
|
LibraryVersion "1.2"
|
|
SourceBlock "xbsIndex_r4/Gateway In"
|
|
SourceType "Xilinx Gateway In Block"
|
|
infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to "
|
|
" Xilinx fixed-point or floating-point data type.<br><br>Hardware notes: In hardware these blocks become top lev"
|
|
"el input ports."
|
|
gui_display_data_type "Boolean"
|
|
arith_type "Boolean"
|
|
n_bits "16"
|
|
bin_pt "14"
|
|
preci_type "Single"
|
|
exp_width "8"
|
|
frac_width "24"
|
|
quantization "Round (unbiased: +/- Inf)"
|
|
overflow "Saturate"
|
|
period "1"
|
|
dbl_ovrd off
|
|
timing_constraint "None"
|
|
locs_specified off
|
|
LOCs "{}"
|
|
UseAsADC off
|
|
ADCChannel "'1'"
|
|
xl_use_area off
|
|
xl_area "[0,0,0,0,0,0,0]"
|
|
inherit_from_input off
|
|
hdl_port "on"
|
|
has_advanced_control "0"
|
|
sggui_pos "20,26,404,607"
|
|
block_type "gatewayin"
|
|
sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
|
|
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0."
|
|
"93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12."
|
|
"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 1"
|
|
"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
|
|
"[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
|
|
"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
|
|
"port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfp"
|
|
"rintf('','COMMENT: end icon text');"
|
|
}
|
|
Block {
|
|
BlockType Reference
|
|
Name "Gaussian Noise\nGenerator"
|
|
SID "8"
|
|
Ports [0, 1]
|
|
Position [175, 273, 255, 317]
|
|
ZOrder 142
|
|
LibraryVersion "1.74"
|
|
SourceBlock "commnoisgen2/Gaussian Noise\nGenerator"
|
|
SourceType "Gaussian Noise Generator"
|
|
m "0"
|
|
d "0.1"
|
|
s "123"
|
|
Ts "0.1"
|
|
frameBased off
|
|
sampPerFrame "1"
|
|
orient off
|
|
outDataType "double"
|
|
}
|
|
Block {
|
|
BlockType Scope
|
|
Name "Scope"
|
|
SID "19"
|
|
Ports [4]
|
|
Position [825, 65, 910, 240]
|
|
ZOrder 151
|
|
Floating off
|
|
Location [75, 57, 1355, 760]
|
|
Open off
|
|
NumInputPorts "4"
|
|
ZoomMode "xonly"
|
|
List {
|
|
ListType AxesTitles
|
|
axes1 "%<SignalLabel>"
|
|
axes2 "%<SignalLabel>"
|
|
axes3 "%<SignalLabel>"
|
|
axes4 "%<SignalLabel>"
|
|
}
|
|
List {
|
|
ListType ScopeGraphics
|
|
FigureColor "[0.5 0.5 0.5]"
|
|
AxesColor "[0 0 0]"
|
|
AxesTickColor "[1 1 1]"
|
|
LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
|
|
LineStyles "-|-|-|-|-|-"
|
|
LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]"
|
|
MarkerStyles "none|none|none|none|none|none"
|
|
}
|
|
ShowLegends off
|
|
YMin "-3~-0.1~-0.1~-50"
|
|
YMax "4~1.1~1.1~50"
|
|
LimitDataPoints off
|
|
}
|
|
Block {
|
|
BlockType Scope
|
|
Name "Scope1"
|
|
SID "23"
|
|
Ports [3]
|
|
Position [440, 363, 515, 457]
|
|
ZOrder 151
|
|
Floating off
|
|
Location [75, 57, 1355, 760]
|
|
Open off
|
|
NumInputPorts "3"
|
|
ZoomMode "xonly"
|
|
List {
|
|
ListType AxesTitles
|
|
axes1 "%<SignalLabel>"
|
|
axes2 "%<SignalLabel>"
|
|
axes3 "%<SignalLabel>"
|
|
}
|
|
List {
|
|
ListType ScopeGraphics
|
|
FigureColor "[0.5 0.5 0.5]"
|
|
AxesColor "[0 0 0]"
|
|
AxesTickColor "[1 1 1]"
|
|
LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
|
|
LineStyles "-|-|-|-|-|-"
|
|
LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]"
|
|
MarkerStyles "none|none|none|none|none|none"
|
|
}
|
|
ShowLegends off
|
|
YMin "-3~-0.1~-0.1"
|
|
YMax "4~1.1~1.1"
|
|
SaveName "ScopeData1"
|
|
LimitDataPoints off
|
|
}
|
|
Block {
|
|
BlockType DiscretePulseGenerator
|
|
Name "Senal Original\n"
|
|
SID "10"
|
|
Ports [0, 1]
|
|
Position [80, 184, 110, 216]
|
|
ZOrder 140
|
|
NamePlacement "alternate"
|
|
PulseType "Time based"
|
|
Period "500"
|
|
PulseWidth "50"
|
|
Port {
|
|
PortNumber 1
|
|
Name "Original"
|
|
RTWStorageClass "Auto"
|
|
DataLoggingNameMode "SignalName"
|
|
}
|
|
}
|
|
Block {
|
|
BlockType Reference
|
|
Name "Senial Interna"
|
|
SID "20"
|
|
Ports [1, 1]
|
|
Position [690, 210, 750, 230]
|
|
ZOrder 147
|
|
LibraryVersion "1.2"
|
|
SourceBlock "xbsIndex_r4/Gateway Out"
|
|
SourceType "Xilinx Gateway Out Block"
|
|
infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
|
|
"pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes: In hardware these blocks become top"
|
|
" level output ports or are discarded, depending on how they are configured."
|
|
inherit_from_input off
|
|
hdl_port on
|
|
timing_constraint "None"
|
|
locs_specified off
|
|
LOCs "{}"
|
|
UseAsDAC off
|
|
DACChannel "'1'"
|
|
xl_use_area off
|
|
xl_area "[0,0,0,0,0,0,0]"
|
|
has_advanced_control "0"
|
|
sggui_pos "20,26,403,629"
|
|
block_type "gatewayout"
|
|
sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
|
|
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
|
|
"93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
|
|
"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
|
|
"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
|
|
"[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
|
|
"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
|
|
"port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
|
|
"printf('','COMMENT: end icon text');"
|
|
Port {
|
|
PortNumber 1
|
|
Name "Interna"
|
|
RTWStorageClass "Auto"
|
|
DataLoggingNameMode "SignalName"
|
|
}
|
|
}
|
|
Block {
|
|
BlockType Reference
|
|
Name "Senial Regenerada\n"
|
|
SID "14"
|
|
Ports [1, 1]
|
|
Position [690, 165, 750, 185]
|
|
ZOrder 147
|
|
LibraryVersion "1.2"
|
|
SourceBlock "xbsIndex_r4/Gateway Out"
|
|
SourceType "Xilinx Gateway Out Block"
|
|
infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
|
|
"pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes: In hardware these blocks become top"
|
|
" level output ports or are discarded, depending on how they are configured."
|
|
inherit_from_input off
|
|
hdl_port on
|
|
timing_constraint "None"
|
|
locs_specified off
|
|
LOCs "{}"
|
|
UseAsDAC off
|
|
DACChannel "'1'"
|
|
xl_use_area off
|
|
xl_area "[0,0,0,0,0,0,0]"
|
|
has_advanced_control "0"
|
|
sggui_pos "20,26,388,578"
|
|
block_type "gatewayout"
|
|
sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
|
|
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
|
|
"93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
|
|
"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
|
|
"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
|
|
"[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
|
|
"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
|
|
"port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
|
|
"printf('','COMMENT: end icon text');"
|
|
Port {
|
|
PortNumber 1
|
|
Name "Regenerada"
|
|
RTWStorageClass "Auto"
|
|
DataLoggingNameMode "SignalName"
|
|
}
|
|
}
|
|
Block {
|
|
BlockType Reference
|
|
Name "Senial Ruidosa"
|
|
SID "21"
|
|
Ports [1, 1]
|
|
Position [690, 120, 750, 140]
|
|
ZOrder 147
|
|
LibraryVersion "1.2"
|
|
SourceBlock "xbsIndex_r4/Gateway Out"
|
|
SourceType "Xilinx Gateway Out Block"
|
|
infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
|
|
"pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes: In hardware these blocks become top"
|
|
" level output ports or are discarded, depending on how they are configured."
|
|
inherit_from_input off
|
|
hdl_port on
|
|
timing_constraint "None"
|
|
locs_specified off
|
|
LOCs "{}"
|
|
UseAsDAC off
|
|
DACChannel "'1'"
|
|
xl_use_area off
|
|
xl_area "[0,0,0,0,0,0,0]"
|
|
has_advanced_control "0"
|
|
sggui_pos "20,26,403,629"
|
|
block_type "gatewayout"
|
|
sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
|
|
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
|
|
"93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
|
|
"22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
|
|
"2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
|
|
"[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
|
|
"9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
|
|
"port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
|
|
"printf('','COMMENT: end icon text');"
|
|
Port {
|
|
PortNumber 1
|
|
Name "Ruido Digital"
|
|
RTWStorageClass "Auto"
|
|
DataLoggingNameMode "SignalName"
|
|
}
|
|
}
|
|
Block {
|
|
BlockType Sum
|
|
Name "Sum"
|
|
SID "13"
|
|
Ports [2, 1]
|
|
Position [295, 190, 315, 210]
|
|
ZOrder 141
|
|
ShowName off
|
|
IconShape "round"
|
|
Inputs "|++"
|
|
InputSameDT off
|
|
OutDataTypeStr "Inherit: Inherit via internal rule"
|
|
SaturateOnIntegerOverflow off
|
|
Port {
|
|
PortNumber 1
|
|
Name "Senal con ruido"
|
|
RTWStorageClass "Auto"
|
|
DataLoggingNameMode "SignalName"
|
|
}
|
|
}
|
|
Line {
|
|
SrcBlock "Gaussian Noise\nGenerator"
|
|
SrcPort 1
|
|
Points [45, 0]
|
|
DstBlock "Sum"
|
|
DstPort 2
|
|
}
|
|
Line {
|
|
Name "Original"
|
|
Labels [0, 0]
|
|
SrcBlock "Senal Original\n"
|
|
SrcPort 1
|
|
Points [30, 0]
|
|
Branch {
|
|
Labels [-1, 0]
|
|
DstBlock "Aumento del Risetime"
|
|
DstPort 1
|
|
}
|
|
Branch {
|
|
Points [0, 240]
|
|
DstBlock "Scope1"
|
|
DstPort 3
|
|
}
|
|
}
|
|
Line {
|
|
Name "Limitada en BW"
|
|
Labels [0, 0]
|
|
SrcBlock "Aumento del Risetime"
|
|
SrcPort 1
|
|
Points [20, 0]
|
|
Branch {
|
|
DstBlock "Sum"
|
|
DstPort 1
|
|
}
|
|
Branch {
|
|
Points [0, 210]
|
|
DstBlock "Scope1"
|
|
DstPort 2
|
|
}
|
|
}
|
|
Line {
|
|
SrcBlock "Filtro"
|
|
SrcPort 1
|
|
DstBlock "Senial Regenerada\n"
|
|
DstPort 1
|
|
}
|
|
Line {
|
|
SrcBlock "Gateway In"
|
|
SrcPort 1
|
|
Points [23, 0]
|
|
Branch {
|
|
DstBlock "Filtro"
|
|
DstPort 1
|
|
}
|
|
Branch {
|
|
Points [0, -70]
|
|
DstBlock "Senial Ruidosa"
|
|
DstPort 1
|
|
}
|
|
}
|
|
Line {
|
|
Name "Regenerada"
|
|
Labels [0, 0]
|
|
SrcBlock "Senial Regenerada\n"
|
|
SrcPort 1
|
|
DstBlock "Scope"
|
|
DstPort 3
|
|
}
|
|
Line {
|
|
Name "Senal con ruido"
|
|
Labels [0, 0]
|
|
SrcBlock "Sum"
|
|
SrcPort 1
|
|
Points [30, 0]
|
|
Branch {
|
|
DstBlock "Gateway In"
|
|
DstPort 1
|
|
}
|
|
Branch {
|
|
Points [0, -115]
|
|
DstBlock "Scope"
|
|
DstPort 1
|
|
}
|
|
Branch {
|
|
Points [0, 180]
|
|
DstBlock "Scope1"
|
|
DstPort 1
|
|
}
|
|
}
|
|
Line {
|
|
SrcBlock "Filtro"
|
|
SrcPort 2
|
|
DstBlock "Convert"
|
|
DstPort 1
|
|
}
|
|
Line {
|
|
Name "Interna"
|
|
Labels [0, 0]
|
|
SrcBlock "Senial Interna"
|
|
SrcPort 1
|
|
DstBlock "Scope"
|
|
DstPort 4
|
|
}
|
|
Line {
|
|
Name "Ruido Digital"
|
|
Labels [0, 0]
|
|
SrcBlock "Senial Ruidosa"
|
|
SrcPort 1
|
|
DstBlock "Scope"
|
|
DstPort 2
|
|
}
|
|
Line {
|
|
SrcBlock "Convert"
|
|
SrcPort 1
|
|
DstBlock "Senial Interna"
|
|
DstPort 1
|
|
}
|
|
}
|
|
}
|
|
MatData {
|
|
NumRecords 1
|
|
DataRecord {
|
|
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|
|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
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|
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|
|
"S N.3,S,S,S(# N,C S.3(R(# N,30Q,3<V(%TI.PIP871C:\"A;,3(N,3,W-2 T.\"XS,2 S-RXX,2 R-RXS,2 Q-BXX,2 Q+C8S-S4@,3(N,3,W-"
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