fdiniello/HDLfilter
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This commit is contained in:
epilef
2017-03-08 09:27:39 -03:00
parent 26dc3504db
commit 9a850c28e4
10 changed files with 469 additions and 275 deletions
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11
FiltroHDL/Filter.vhd
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@@ -1,7 +1,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.array_functions.all;
use work.filter_pkg.all;
entity Filter is
generic (
@@ -10,7 +10,7 @@ entity Filter is
SIMETRIC : boolean := TRUE;
CONSTANTS : array_of_integers := (-10,-9,-8,-7,-6,-5,-4,3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20)
CONSTANTS : array_of_integers := (-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8)
);
port (
@@ -19,7 +19,8 @@ entity Filter is
reset: in std_logic;
d_i : in std_logic;
d_o : out std_logic
d_o : out std_logic;
p_o : out std_logic_vector(9 downto 0)
);
end Filter;
@@ -49,6 +50,7 @@ architecture Behavioral of Filter is
signal d_s : std_logic := '0';
signal p_s : std_logic_vector(9 downto 0) := (others => '0');
type STATUS_T is ( wait_start,
clear,
@@ -62,6 +64,7 @@ architecture Behavioral of Filter is
begin
d_o <= d_s;
p_o <= p_s;
--~ Proceso sincrónico para cambio de estados
stateProcess:
@@ -145,6 +148,8 @@ begin
begin
if ( rising_edge(clk_i) ) then
if ( enable = '1' and sample_clk_s = '1' and i = N-1 ) then
p_s <= std_logic_vector(to_signed(accum,p_s'length));
if ( accum > 0 ) then
d_s <= '1';
else