50 lines
797 B
VHDL
50 lines
797 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.filter_pkg.all;
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entity FilterWrapper is
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generic (
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CLK_FREQ : integer := 50e6;
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DATA_RATE: integer := 250e3;
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SIMETRIC : boolean := TRUE;
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CONSTANTS : array_of_integers := (-4,-3,-2,-1,0,1,2,3,4,5)
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);
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port (
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clk : in std_logic;
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ce: in std_logic;
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d_i : in std_logic;
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d_o : out std_logic;
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p_o : out std_logic_vector(9 downto 0)
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);
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end FilterWrapper;
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architecture Behavioral of FilterWrapper is
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begin
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uut: Filter Generic Map(
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CLK_FREQ => CLK_FREQ,
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DATA_RATE => DATA_RATE,
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SIMETRIC => SIMETRIC,
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CONSTANTS => CONSTANTS
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)
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PORT MAP (
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clk_i => clk,
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enable => ce,
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reset => '0',
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d_i => d_i,
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d_o => d_o,
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p_o => p_o
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);
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end Behavioral;
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